公开(公告)号：EP4250561A1

公开(公告)日：2023-09-27

申请号：EP23159134.8

申请日：2023-02-28

Applicant: STMicroelectronics S.r.l.

Inventor： ROGLEDI, Nicola ,  POLETTO, Vanni ,  LEONE, Antonio Davide

IPC: H03F3/45 ,  H03G1/00 ,  G01S15/93

Abstract: A circuit arrangement of an amplifier with currentcontrolled gain, said circuit arrangement (30; 40; 50) having a symmetrical differential structure, comprising a differential input stage (21), which includes, on each differential branch, an input transistor, in particular a MOSFET (M1, M2), coupled, in particular through an input resistance ( R I ), to an input node (NI), there being set between said input node (N1) and ground (GND) a current generator (22) for biasing the input stage (21) that supplies, said input stage (21) being configured for operating with a constant input biasing, an input voltage (Vin) being applied between the inputs of the input transistors (M1, M2), a drain electrode of the input transistor (M1) being coupled to the supply voltage (Vss) through a respective diode (D1, D2), as well as to a differential output amplification stage (23) having bipolar transistors (T1, T2) with coupled emitters, there being coupled to said emitters a current generator (24) for biasing the output stage (23, 33) which generates an output current ( I bOUT ) and comprises, on each differential branch, a bipolar transistor (T1, T2; B2) biased in the active region, the base electrode of which is coupled to the drain electrode of the input transistor (M1, M2) and the collector electrode of which is coupled to the supply voltage (Vss), while coupled to its emitter electrode is a current generator (24) for biasing the output stage (23, 33) which generates an output current ( I bOUT ) , an output voltage (Vout) being drawn from between the collectors of the bipolar transistors (T1, T2), said output stage (23, 33) being configured with constant output biasing,
said circuit arrangement being configured for controlling a gain between the input and the output by controlling the values of input and output biasing current;
said circuit arrangement (30) being configured for supplying a first reference current ( I d ) and a second reference current ( I n ) having complementary values such that their sum is constant, the value of said input biasing current ( I bIN ) corresponding to the first reference current ( I d ), and the output biasing current ( I bOUT ) corresponding to the sum ( I d + I n ) of said first reference current ( I d ) and said second reference current ( I n ).

公开(公告)号：EP4207604A1

公开(公告)日：2023-07-05

申请号：EP22211363.1

申请日：2022-12-05

Applicant: STMicroelectronics S.r.l.

Inventor： POLETTO, Vanni ,  ROGLEDI, Nicola ,  LEONE, Antonio Davide

IPC: H03M3/00 ,  H03M1/36

Abstract: An analog to digital converter apparatus, adapt to receive a continuous input signal (Vdiff; Vi+,V-,i+,i-),
comprising an integrating block (11; 11, 12), comprising at least an integrating stage, which output is coupled to a flash analog to digital converter (13; 33),
said analog to digital converter apparatus comprising a feedback path (15; 151, 152; 35; 351, 352) coupled to the output (DO) of said flash analog to digital converter (13; 33), said feedback path comprising at least a digital to analog conversion block (15; 151, 152; 35; 351, 352) which output (Vfeed; II, 12) is compared (21; 21, 22) at least to the input signal (Vdiff; Vi+,V-,i+,i-) to obtain an error signal (Ev; Ev; Ev2) which is brought as input to said integrating block (11; 11, 12),
wherein a control block (34) configured to perform a control comprising at least a digital integration (343), is coupled between the output of said flash analog to digital converter (33) and said feedback path (35; 351, 352).

公开(公告)号：EP3203247A1

公开(公告)日：2017-08-09

申请号：EP16191022.9

申请日：2016-09-28

Applicant: STMicroelectronics S.r.l.

Inventor： POLETTO, Vanni ,  ROGLEDI, Nicola

IPC: G01R27/14

CPC classification number: G01R27/14

Abstract: A device for measuring an unknown resistance (R X ), comprising a reference resistance (R REF ) in series with the unknown resistance (R X ). The device is prearranged for measuring a first voltage (V1) and a second voltage (V2), across the reference resistance (R REF ) and of the unknown resistance (R X ), respectively.
The device comprises changeover-switch modules (muxA, muxB), which receive at input the first voltage (V1) and the second voltage (V2) and supply values (D1, D2) representing the first voltage (V1) and the second voltage (V2), and a single analog-to-digital converter (ADC), which supplies at output the digital representation (D X ) of the value of the unknown resistance (R X ) as ratio between the values (D1, D2) at input to the converter (ADC). The analog-to-digital converter (ADC) contains two negative feedback loops (D2, D1), which function in an alternative way according to the outputs of the changeover-switch modules (muxA, muxB). The negative feedback loops (D2, D1) are first-order continuous-time sigma-delta converters. In particular, one of the two sigma-delta converters has a constant digital output at the level "1".

Abstract translation: 一种测量未知电阻（RX）的装置，包括与未知电阻（RX）串联的参考电阻（RREF）。 该装置被预先设定用于分别跨参考电阻（RREF）和未知电阻（RX）测量第一电压（V1）和第二电压（V2）。 该装置包括在输入端接收第一电压（V1）和第二电压（V2）以及表示第一电压（V1）和第二电压（V1）的电源值（D1，D2）的切换开关模块（muxA，muxB） V2）和单个模数转换器（ADC），其在输出端提供未知电阻值（RX）的数字表示（DX），作为输入端处的值（D1，D2）与 转换器（ADC）。 模数转换器（ADC）包含两个负反馈环路（D2，D1），根据转换开关模块（muxA，muxB）的输出以另一种方式工作。 负反馈回路（D2，D1）是一阶连续时间Σ-Δ转换器。 特别是，两个西格玛 - 德尔塔转换器中的一个在水平“1”处具有恒定的数字输出。