Regulator of a digital-to-analog converter and relative converter
    1.
    发明公开
    Regulator of a digital-to-analog converter and relative converter 审中-公开
    Vorrichtung und Verfahren zur Regelung eines D / A-Wandlers

    公开(公告)号:EP1830468A1

    公开(公告)日:2007-09-05

    申请号:EP06425144.0

    申请日:2006-03-03

    CPC classification number: H03M1/0607 H03M1/785

    Abstract: A description has been given of a regulator for a digital-to-analog converter having in input a digital signal (BUS ) and being suitable for providing an analog signal (Vout) in output. The regulator comprises at least one pair of buffers (Buf1, Buf2..Bufn) having in input said digital signal (BUS ) and the outputs connected to a pair of circuit branches (r1, r2..rn) connected to the output of the regulator; each of said at least two circuit branches comprises at least one resistance. To at least one (Buf2, Buf3...Bufn)) of said at least one pair of buffers a variable resistance (Rv2...Rvn) is associated and the regulator comprises means (10) having in input the analog signal and being suitable for measuring its trend and acting on the variable resistance (Rv2...Rvn) in response to its possible anomalous trend compared to a desired trend.

    Abstract translation: 已经给出了一种用于数模转换器的稳压器的描述,该数模转换器具有输入数字信号(BUS i)并且适于在输出中提供模拟信号(Vout)。 调节器包括至少一对缓冲器(Buf1,Buf2..Bufn),其中输入了所述数字信号(BUSI),并且输出端连接到一对电路分支(r1,r2..rn) 调节器输出; 所述至少两个电路分支中的每一个包括至少一个电阻。 对于所述至少一对缓冲器中的至少一个(Buf2,Buf3 ... Bufn),可变电阻(Rv2 ... Rvn)相关联,并且调节器包括在输入模拟信号并且为 适合于测量其趋势并作用于可变电阻(Rv2 ... Rvn),以响应与期望趋势相比可能的异常趋势。

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