公开(公告)号：EP1670002A1

公开(公告)日：2006-06-14

申请号：EP05025286.5

申请日：2005-11-18

Applicant: STMicroelectronics S.r.l.

Inventor： Cascone, Davide ,  Del Gatto, Nicola ,  Confalonieri, Emanuele ,  Mollichelli, Massimiliano

IPC: G11C16/30

CPC classification number: G11C16/30

Abstract: A method for configuring a voltage regulator (20) connected to a memory cell (1) is described, the method comprising the steps of:

identifying at least a first and a second operation regions of the cell (1);
associating the first and second operation regions with respective first and second operation conditions of the cell (1);
detecting an operative condition of the cell (1) involved in a programming operation;
generating at least a configuration signal (EN_LOW_IPROG_HV) of the regulator according to said detected operative condition, this configuration signal (EN_LOW_IPROG_HV) taking a first and a second value associated with the first and second operation conditions.

Abstract translation: 描述了一种用于配置连接到存储单元（1）的电压调节器（20）的方法，该方法包括以下步骤：识别单元（1）的至少第一和第二操作区域; 将所述第一和第二操作区域与所述单元（1）的各自的第一和第二操作条件相关联; 检测参与编程操作的单元（1）的操作状态; 根据所述检测到的操作条件至少产生调节器的配置信号（EN_LOW_IPROG_HV），该配置信号（EN_LOW_IPROG_HV）取第一和第二值与第一和第二操作条件相关联。

公开(公告)号：EP1858027A1

公开(公告)日：2007-11-21

申请号：EP06114228.7

申请日：2006-05-19

Applicant: STMicroelectronics S.r.l.

Inventor： Di Vincenzo, Umberto ,  Versari, Roberto ,  Mollichelli, Massimiliano

IPC: G11C16/26 ,  G11C16/28 ,  G11C7/06 ,  G11C16/24 ,  G11C7/12

CPC classification number: G11C16/26 ,  G11C7/067 ,  G11C7/12 ,  G11C16/24 ,  G11C16/28 ,  G11C2207/063

Abstract: A sensing circuit is provided. The sensing circuit is adapted to determine when a cell current flowing trough a selected memory cell exceeds a reference current during an evaluation phase of a sensing operation. The sensing circuit is adapted to be coupled to at least one selected memory cell through a respective bit line. The sensing circuit includes: an access circuit node adapted to be coupled to the bit line; precharging means adapted to be activated in a precharge phase of the sensing operation preceding the evaluation phase, so as to bring a voltage of said access circuit node to a reference voltage; a reference circuit node coupled to the access circuit node and arranged to receive the reference current. The sensing circuit further includes an evaluation circuit node coupled to the reference circuit node through a first current to voltage converter, adapted to sink a current flowing from the reference circuit node to the evaluation circuit node and to produce a corresponding voltage difference between the reference circuit node and the evaluation circuit node, wherein said current is nearly equal to the reference current substantially at the end of the precharge phase; comparator means are provided, adapted to compare the voltage of the access circuit node with the voltage of the evaluation circuit node and to provide a corresponding comparison signal whose time pattern indicates when the cell current exceeds the reference current. The first current to voltage converter is an electronic device having essentially the behavior of a diode.

Abstract translation: 提供感测电路。 感测电路适于确定在感测操作的评估阶段期间流经所选择的存储器单元的单元电流何时超过参考电流。 感测电路适于通过相应的位线耦合到至少一个选定的存储器单元。 感测电路包括：适于耦合到位线的接入电路节点; 预充电装置，其适于在所述评估阶段之前的所述感测操作的预充电阶段中被激活，以使所述访问电路节点的电压为参考电压; 参考电路节点，其耦合到所述接入电路节点并被布置成接收所述参考电流。 感测电路还包括通过第一电流 - 电压转换器耦合到参考电路节点的评估电路节点，适用于吸收从参考电路节点流向评估电路节点的电流，并产生参考电路之间的相应电压差 节点和评估电路节点，其中所述电流几乎等于基本上在预充电阶段结束时的参考电流; 提供比较器装置，用于将访问电路节点的电压与评估电路节点的电压进行比较，并提供对应的比较信号，其时间模式指示电池电流何时超过参考电流。 第一个电流到电压转换器是具有基本上二极管行为的电子器件。

公开(公告)号：EP1830468A1

公开(公告)日：2007-09-05

申请号：EP06425144.0

申请日：2006-03-03

Applicant: STMicroelectronics S.r.l.

Inventor： Versari, Roberto ,  Mollichelli, Massimiliano ,  Del Gatto, Nicola ,  Rosito, Nicola ,  Confalonieri, Emanuele

IPC: H03M1/06

CPC classification number: H03M1/0607 ,  H03M1/785

Abstract: A description has been given of a regulator for a digital-to-analog converter having in input a digital signal (BUS ) and being suitable for providing an analog signal (Vout) in output. The regulator comprises at least one pair of buffers (Buf1, Buf2..Bufn) having in input said digital signal (BUS ) and the outputs connected to a pair of circuit branches (r1, r2..rn) connected to the output of the regulator; each of said at least two circuit branches comprises at least one resistance. To at least one (Buf2, Buf3...Bufn)) of said at least one pair of buffers a variable resistance (Rv2...Rvn) is associated and the regulator comprises means (10) having in input the analog signal and being suitable for measuring its trend and acting on the variable resistance (Rv2...Rvn) in response to its possible anomalous trend compared to a desired trend.

Abstract translation: 已经给出了一种用于数模转换器的稳压器的描述，该数模转换器具有输入数字信号（BUS i）并且适于在输出中提供模拟信号（Vout）。 调节器包括至少一对缓冲器（Buf1，Buf2..Bufn），其中输入了所述数字信号（BUSI），并且输出端连接到一对电路分支（r1，r2..rn） 调节器输出; 所述至少两个电路分支中的每一个包括至少一个电阻。 对于所述至少一对缓冲器中的至少一个（Buf2，Buf3 ... Bufn），可变电阻（Rv2 ... Rvn）相关联，并且调节器包括在输入模拟信号并且为 适合于测量其趋势并作用于可变电阻（Rv2 ... Rvn），以响应与期望趋势相比可能的异常趋势。

公开(公告)号：EP1646051B1

公开(公告)日：2008-03-05

申请号：EP04425754.1

申请日：2004-10-08

Applicant: STMicroelectronics S.r.l.

Inventor： Sforzin, Marco ,  Del Gatto, Nicola ,  Mollichelli, Massimiliano ,  Scotti, Massimiliano

IPC: G11C16/24

CPC classification number: G11C16/24 ,  G11C16/30

公开(公告)号：EP1670002B8

公开(公告)日：2008-02-27

申请号：EP05025286.5

申请日：2005-11-18

Applicant: STMicroelectronics S.r.l.

Inventor： Cascone, Davide ,  Del Gatto, Nicola ,  Confalonieri, Emanuele ,  Mollichelli, Massimiliano

IPC: G11C16/30

CPC classification number: G11C16/30

公开(公告)号：EP1646051A1

公开(公告)日：2006-04-12

申请号：EP04425754.1

申请日：2004-10-08

Applicant: STMicroelectronics S.r.l.

Inventor： Sforzin, Marco ,  Del Gatto, Nicola ,  Mollichelli, Massimiliano ,  Scotti, Massimiliano

IPC: G11C16/24

CPC classification number: G11C16/24 ,  G11C16/30

Abstract: In a memory device (1; 30) having an array (2) of memory cells (3), a column decoder (9) is configured to address the memory cells (3), and a charge-pump supply circuit (6; 32) generates a boosted supply voltage (V b ; V yr ) for the column decoder (9). A connecting stage (22) is arranged between the supply circuit (6; 32) and the column decoder (9); the connecting stage (22) switches between a high-impedance state and a low-impedance state, and is configured to switch into the high-impedance state in given operating conditions of the memory device (1; 30), in particular during a reading step.

Abstract translation: 在存储装置（1; 30），其具有在（2）的存储单元（3）阵列，列解码器（9）被配置为处理存储单元（3），和一个电荷泵电源电路（6; 32 ）生成一个升压电源电压（V b;对列译码器（9）V年）。 和列译码器（9）;所述的连接阶段（22）的供电电路（32 6）之间布置; 连接阶段（22）的高阻抗状态和低阻抗状态之间切换，并且被配置为切换到高阻抗状态的存储装置（1; 30）的给定操作条件的读出期间，尤其是 一步。