公开(公告)号：EP1400980A1

公开(公告)日：2004-03-24

申请号：EP02425562.2

申请日：2002-09-17

Applicant: STMicroelectronics S.r.l.

Inventor： Poidomani, Carla ,  Confalonieri, Emanuele ,  Sforzin, Marco ,  Del Gatto, Nicola

IPC: G11C16/24 ,  G11C7/06

CPC classification number: G11C7/062 ,  G11C16/24

Abstract: A circuit (125,130) for biasing an input node (Na) of a sense amplifier (115) is proposed. The circuit includes means (125) for keeping the input node at a pre-set operative voltage during a sensing operation; the circuit of the invention further includes means (250) for pulling the input node from a starting voltage towards a power supply voltage (+Vdd), the operative voltage being comprised between the starting voltage and the power supply voltage, and control means (255) for disabling the means for pulling before the input node reaches the operative voltage.

Abstract translation: 一种用于在读出放大器（115）的输入节点（Na）的偏压电路（125.130）的提议。 该电路包括用于在传感操作保持在预先设定的工作电压的输入节点的装置（125）; 本发明的电路进一步包括：用于从一个起动电压向电源电压（+ VDD），工作电压被包括起始电压和电源电压，和控制装置之间拉动所述输入节点装置（250）（255 ），用于禁止所述用于拉动输入节点达到工作电压之前。

公开(公告)号：EP1686591B1

公开(公告)日：2008-01-09

申请号：EP05100551.0

申请日：2005-01-28

Applicant: STMicroelectronics S.r.l.

Inventor： Sforzin, Marco ,  Del Gatto, Nicola ,  Ferrario, Marco ,  Confalonieri, Emanuele

IPC: G11C16/26 ,  G11C11/56

CPC classification number: G11C16/26

公开(公告)号：EP1670002A1

公开(公告)日：2006-06-14

申请号：EP05025286.5

申请日：2005-11-18

Applicant: STMicroelectronics S.r.l.

Inventor： Cascone, Davide ,  Del Gatto, Nicola ,  Confalonieri, Emanuele ,  Mollichelli, Massimiliano

IPC: G11C16/30

CPC classification number: G11C16/30

Abstract: A method for configuring a voltage regulator (20) connected to a memory cell (1) is described, the method comprising the steps of:

identifying at least a first and a second operation regions of the cell (1);
associating the first and second operation regions with respective first and second operation conditions of the cell (1);
detecting an operative condition of the cell (1) involved in a programming operation;
generating at least a configuration signal (EN_LOW_IPROG_HV) of the regulator according to said detected operative condition, this configuration signal (EN_LOW_IPROG_HV) taking a first and a second value associated with the first and second operation conditions.

Abstract translation: 描述了一种用于配置连接到存储单元（1）的电压调节器（20）的方法，该方法包括以下步骤：识别单元（1）的至少第一和第二操作区域; 将所述第一和第二操作区域与所述单元（1）的各自的第一和第二操作条件相关联; 检测参与编程操作的单元（1）的操作状态; 根据所述检测到的操作条件至少产生调节器的配置信号（EN_LOW_IPROG_HV），该配置信号（EN_LOW_IPROG_HV）取第一和第二值与第一和第二操作条件相关联。

公开(公告)号：EP1830468A1

公开(公告)日：2007-09-05

申请号：EP06425144.0

申请日：2006-03-03

Applicant: STMicroelectronics S.r.l.

Inventor： Versari, Roberto ,  Mollichelli, Massimiliano ,  Del Gatto, Nicola ,  Rosito, Nicola ,  Confalonieri, Emanuele

IPC: H03M1/06

CPC classification number: H03M1/0607 ,  H03M1/785

Abstract: A description has been given of a regulator for a digital-to-analog converter having in input a digital signal (BUS ) and being suitable for providing an analog signal (Vout) in output. The regulator comprises at least one pair of buffers (Buf1, Buf2..Bufn) having in input said digital signal (BUS ) and the outputs connected to a pair of circuit branches (r1, r2..rn) connected to the output of the regulator; each of said at least two circuit branches comprises at least one resistance. To at least one (Buf2, Buf3...Bufn)) of said at least one pair of buffers a variable resistance (Rv2...Rvn) is associated and the regulator comprises means (10) having in input the analog signal and being suitable for measuring its trend and acting on the variable resistance (Rv2...Rvn) in response to its possible anomalous trend compared to a desired trend.

Abstract translation: 已经给出了一种用于数模转换器的稳压器的描述，该数模转换器具有输入数字信号（BUS i）并且适于在输出中提供模拟信号（Vout）。 调节器包括至少一对缓冲器（Buf1，Buf2..Bufn），其中输入了所述数字信号（BUSI），并且输出端连接到一对电路分支（r1，r2..rn） 调节器输出; 所述至少两个电路分支中的每一个包括至少一个电阻。 对于所述至少一对缓冲器中的至少一个（Buf2，Buf3 ... Bufn），可变电阻（Rv2 ... Rvn）相关联，并且调节器包括在输入模拟信号并且为 适合于测量其趋势并作用于可变电阻（Rv2 ... Rvn），以响应与期望趋势相比可能的异常趋势。

公开(公告)号：EP1686591A1

公开(公告)日：2006-08-02

申请号：EP05100551.0

申请日：2005-01-28

Applicant: STMicroelectronics S.r.l.

Inventor： Sforzin, Marco ,  Del Gatto, Nicola ,  Ferrario, Marco ,  Confalonieri, Emanuele

IPC: G11C16/26 ,  G11C11/56

CPC classification number: G11C16/26

Abstract: A memory device (100) is proposed. The memory device includes a plurality of memory cells (Mc) each one for storing a value, at least one reference cell (Mr 0 -Mr 2 ), biasing means (115) for biasing a set of selected memory cells and the at least one reference cell with a biasing voltage (Vc,Vr) having a substantially monotone time pattern, means (130) for detecting the reaching of a threshold value by a current (Ic,Ir) of each selected memory cell and of each reference cell, and means (145) for determining the value stored in each selected memory cell according to a temporal relation of the reaching of the threshold value by the currents of the selected memory cell and of the at least one reference cell. The biasing means includes means (305) for applying a predetermined biasing current (Ib) to the selected memory cells and to the at least one reference cell.

Abstract translation: 一种存储器装置（100）被提议。 所述存储器装置包括存储器单元的用于偏置一组选择的存储单元的多个（MC）每一个用于存储一个值，至少一个参考单元（先生0 -Mr 2），偏压装置（115）和所述至少一个 具有用于每个被选择的存储单元的电流（Ic，Ir）的各基准单元的检测的阈值的到达基本上单调时间图案，装置（130）的偏置电压（VC，VR）参考单元，和 装置（145），用于确定挖掘存储在每个选定存储器单元gemäß阈值的通过和所述至少一个参考单元的选定存储器单元的电流的到达的时间关系的值。 偏压装置包括用于将预定偏置电流（Ib），以所选择的存储器单元和所述至少一个参考蜂窝小区的装置（305）。

公开(公告)号：EP1653474A1

公开(公告)日：2006-05-03

申请号：EP05022651.3

申请日：2005-10-18

Applicant: STMicroelectronics S.r.l.

Inventor： Confalonieri, Emanuele ,  Del Gatto, Nicola ,  Lisi, Carlo ,  Ferrario, Marco

IPC: G11C11/56 ,  G11C5/14 ,  G11C16/30

CPC classification number: G11C8/10 ,  G11C8/18 ,  G11C11/5628 ,  G11C16/10 ,  G11C2211/5621

Abstract: The present invention relates to a method for programming a multilevel memory of the flash EEPROM type comprising a matrix of cells grouped in memory words.
Advantageously according to the invention the method provides the simultaneous generation of a first programming voltage value (V PROG ) and a second verify voltage value (V VER ), suitable to bias word lines (WLS) of the above memory matrix, respectively during programming and verify operations of the memory itself.
The present invention also relates to a circuit implementing the above method.

Abstract translation: 本发明涉及一种用于编程闪存EEPROM类型的多级存储器的方法，包括分组在存储器字中的单元矩阵。 有利地，根据本发明，该方法提供了同时产生适于在编程期间偏置上述存储器矩阵的字线（WLS）的第一编程电压值（V PROG）和第二验证电压值（V VER），以及 验证内存本身的操作。 本发明还涉及实现上述方法的电路。

公开(公告)号：EP1646051B1

公开(公告)日：2008-03-05

申请号：EP04425754.1

申请日：2004-10-08

Applicant: STMicroelectronics S.r.l.

Inventor： Sforzin, Marco ,  Del Gatto, Nicola ,  Mollichelli, Massimiliano ,  Scotti, Massimiliano

IPC: G11C16/24

CPC classification number: G11C16/24 ,  G11C16/30

公开(公告)号：EP1670002B8

公开(公告)日：2008-02-27

申请号：EP05025286.5

申请日：2005-11-18

Applicant: STMicroelectronics S.r.l.

Inventor： Cascone, Davide ,  Del Gatto, Nicola ,  Confalonieri, Emanuele ,  Mollichelli, Massimiliano

IPC: G11C16/30

CPC classification number: G11C16/30

公开(公告)号：EP1670002B1

公开(公告)日：2007-10-03

申请号：EP05025286.5

申请日：2005-11-18

Applicant: STMicroelectronics S.r.l.

Inventor： Cascone, Davide ,  Del Gatto, Nicola ,  Confalonieri, Emanuele , 

IPC: G11C16/30

CPC classification number: G11C16/30

公开(公告)号：EP1646051A1

公开(公告)日：2006-04-12

申请号：EP04425754.1

申请日：2004-10-08

Applicant: STMicroelectronics S.r.l.

Inventor： Sforzin, Marco ,  Del Gatto, Nicola ,  Mollichelli, Massimiliano ,  Scotti, Massimiliano

IPC: G11C16/24

CPC classification number: G11C16/24 ,  G11C16/30

Abstract: In a memory device (1; 30) having an array (2) of memory cells (3), a column decoder (9) is configured to address the memory cells (3), and a charge-pump supply circuit (6; 32) generates a boosted supply voltage (V b ; V yr ) for the column decoder (9). A connecting stage (22) is arranged between the supply circuit (6; 32) and the column decoder (9); the connecting stage (22) switches between a high-impedance state and a low-impedance state, and is configured to switch into the high-impedance state in given operating conditions of the memory device (1; 30), in particular during a reading step.

Abstract translation: 在存储装置（1; 30），其具有在（2）的存储单元（3）阵列，列解码器（9）被配置为处理存储单元（3），和一个电荷泵电源电路（6; 32 ）生成一个升压电源电压（V b;对列译码器（9）V年）。 和列译码器（9）;所述的连接阶段（22）的供电电路（32 6）之间布置; 连接阶段（22）的高阻抗状态和低阻抗状态之间切换，并且被配置为切换到高阻抗状态的存储装置（1; 30）的给定操作条件的读出期间，尤其是 一步。