Abstract:
A successive approximation register having a serial input (CM) and output (DO) comprises a chain of logic circuits of the bistable type which have selectable input terminals (FF4,FF3,FF2,FF1) feedback connected by a storage and control element (FF-s) and logic gate circuits (OR1,OR2,OR3) of the OR type, and connected to a serial line through respective internal switches (TG1) communicating the serial line to input terminals (S) of the logic circuits in said chain, the serial line forming an input to a flip-flop (FFD) of the D type which is the output element of the register.