Successive approximation register having serial input and output
    1.
    发明公开
    Successive approximation register having serial input and output 失效
    注册sch itt we iser iser iser iser。。。。。。。。。。

    公开(公告)号:EP0889598A1

    公开(公告)日:1999-01-07

    申请号:EP97830326.1

    申请日:1997-06-30

    CPC classification number: H03M1/462

    Abstract: A successive approximation register having a serial input (CM) and output (DO) comprises a chain of logic circuits of the bistable type which have selectable input terminals (FF4,FF3,FF2,FF1) feedback connected by a storage and control element (FF-s) and logic gate circuits (OR1,OR2,OR3) of the OR type, and connected to a serial line through respective internal switches (TG1) communicating the serial line to input terminals (S) of the logic circuits in said chain, the serial line forming an input to a flip-flop (FFD) of the D type which is the output element of the register.

    Abstract translation: 具有串行输入(CM)和输出(DO)的逐次逼近寄存器包括具有由存储和控制元件(FF)连接的可选输入端(FF4,FF3,FF2,FF1)反馈的双稳态类型的逻辑电路链 -s)和逻辑门电路(OR1,OR2,OR3),并且通过将串行线路传送到所述链路中的逻辑电路的输入端子(S)的相应内部开关(TG1)连接到串行线路, 该串行线形成作为寄存器的输出元件的D型触发器(FFD)的输入。

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