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1.发明公开A toggle flip-flop with a reduced integration area 失效Kippschaltung mit reduzierterIntegrationsfläche
公开(公告)号：EP0899878A1
公开(公告)日：1999-03-03
申请号：EP97830432.7
申请日：1997-08-29
Applicant: STMicroelectronics S.r.l.
Inventor： Rossi, Annamaria , Fucili, Giona , Cane, Marcello , Nessi, Maurizio
CPC classification number: H03K3/037 , H03K3/356113
Abstract: A toggle flip-flop (FFT) with reduced integration area, comprising a flip-flop of the D type with an inverting input stage (T,A,B,C) and a master-slave portion.
Three transistors (M 1 ,M 2 ,M 3 ) connected to the inverting stage form a logic gate of the XOR type whereto the output terminal (Q) of the master-slave portion is fed back.Abstract translation: 具有减小的积分区域的切换触发器（FFT）包括具有反相输入级（T，A，B，C）的D型触发器和主从部分。 连接到反相级的三个晶体管（M1，M2，M3）形成XOR类型的逻辑门，对主从部分的输出端（Q）进行反馈。
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Patent Agency Ranking2.发明授权Row decoding circuit for a semiconductor non-volatile electrically programmable memory, and corresponding method 失效Zellendekodiererschaltkreis为非易失性的电可编程存储器和相应的方法
公开(公告)号：EP0798735B1
公开(公告)日：2004-07-28
申请号：EP96830174.7
申请日：1996-03-29
Applicant: STMicroelectronics S.r.l.
Inventor： Tassan Caser, Fabio , Sali, Mauro , Cane, Marcello
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3.发明公开Successive approximation register having serial input and output 失效注册sch itt we iser iser iser iser。。。。。。。。。。
公开(公告)号：EP0889598A1
公开(公告)日：1999-01-07
申请号：EP97830326.1
申请日：1997-06-30
Applicant: STMicroelectronics S.r.l.
Inventor： Rossi, Annamari , Fucili, Giona , Cane, Marcello , Nessi, Maurizio
IPC: H03M1/38
CPC classification number: H03M1/462
Abstract: A successive approximation register having a serial input (CM) and output (DO) comprises a chain of logic circuits of the bistable type which have selectable input terminals (FF4,FF3,FF2,FF1) feedback connected by a storage and control element (FF-s) and logic gate circuits (OR1,OR2,OR3) of the OR type, and connected to a serial line through respective internal switches (TG1) communicating the serial line to input terminals (S) of the logic circuits in said chain, the serial line forming an input to a flip-flop (FFD) of the D type which is the output element of the register.
Abstract translation: 具有串行输入（CM）和输出（DO）的逐次逼近寄存器包括具有由存储和控制元件（FF）连接的可选输入端（FF4，FF3，FF2，FF1）反馈的双稳态类型的逻辑电路链 -s）和逻辑门电路（OR1，OR2，OR3），并且通过将串行线路传送到所述链路中的逻辑电路的输入端子（S）的相应内部开关（TG1）连接到串行线路， 该串行线形成作为寄存器的输出元件的D型触发器（FFD）的输入。
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4.发明授权Erase voltage control circuit for an electrically erasable non-volatile memory cell 失效擦除电压控制电路，用于可擦除，非易失性存储器单元
公开(公告)号：EP0786779B1
公开(公告)日：2004-07-28
申请号：EP96830025.1
申请日：1996-01-24
Applicant: STMicroelectronics S.r.l.
Inventor： Villa, Corrado , Dallabora, Marco , Cane, Marcello
IPC: G11C16/06
CPC classification number: G11C16/14
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公开(公告)号：EP0899878B1
公开(公告)日：2003-11-05
申请号：EP97830432.7
申请日：1997-08-29
Applicant: STMicroelectronics S.r.l.
Inventor： Rossi, Annamaria , Fucili, Giona , Cane, Marcello , Nessi, Maurizio
CPC classification number: H03K3/037 , H03K3/356113
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6.发明授权Voltage regulator for semiconductor non-volatile electrically programmable memory devices 失效电压调节器为非易失性的，电可编程半导体存储器设备
公开(公告)号：EP0766256B1
公开(公告)日：1999-12-01
申请号：EP95830407.3
申请日：1995-09-29
Applicant: STMicroelectronics S.r.l.
Inventor： Tassan Caser, Fabio , Schippers, Stefan , Cane, Marcello
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