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    A toggle flip-flop with a reduced integration area
    4.
    发明公开
    A toggle flip-flop with a reduced integration area 失效
    Kippschaltung mit reduzierterIntegrationsfläche

    公开(公告)号：EP0899878A1

    公开(公告)日：1999-03-03

    申请号：EP97830432.7

    申请日：1997-08-29

    Applicant: STMicroelectronics S.r.l.

    Inventor： Rossi, Annamaria ,  Fucili, Giona ,  Cane, Marcello ,  Nessi, Maurizio

    IPC: H03K3/00 ,  H03K3/356 ,  H03K3/037

    CPC classification number: H03K3/037 ,  H03K3/356113

    Abstract: A toggle flip-flop (FFT) with reduced integration area, comprising a flip-flop of the D type with an inverting input stage (T,A,B,C) and a master-slave portion.
    Three transistors (M 1 ,M 2 ,M 3 ) connected to the inverting stage form a logic gate of the XOR type whereto the output terminal (Q) of the master-slave portion is fed back.

    Abstract translation: 具有减小的积分区域的切换触发器（FFT）包括具有反相输入级（T，A，B，C）的D型触发器和主从部分。 连接到反相级的三个晶体管（M1，M2，M3）形成XOR类型的逻辑门，对主从部分的输出端（Q）进行反馈。

    Successive approximation register having serial input and output
    5.
    发明公开
    Successive approximation register having serial input and output 失效
    注册sch itt we iser iser iser iser。。。。。。。。。。

    公开(公告)号：EP0889598A1

    公开(公告)日：1999-01-07

    申请号：EP97830326.1

    申请日：1997-06-30

    Applicant: STMicroelectronics S.r.l.

    Inventor： Rossi, Annamari ,  Fucili, Giona ,  Cane, Marcello ,  Nessi, Maurizio

    IPC: H03M1/38

    CPC classification number: H03M1/462

    Abstract: A successive approximation register having a serial input (CM) and output (DO) comprises a chain of logic circuits of the bistable type which have selectable input terminals (FF4,FF3,FF2,FF1) feedback connected by a storage and control element (FF-s) and logic gate circuits (OR1,OR2,OR3) of the OR type, and connected to a serial line through respective internal switches (TG1) communicating the serial line to input terminals (S) of the logic circuits in said chain, the serial line forming an input to a flip-flop (FFD) of the D type which is the output element of the register.

    Abstract translation: 具有串行输入（CM）和输出（DO）的逐次逼近寄存器包括具有由存储和控制元件（FF）连接的可选输入端（FF4，FF3，FF2，FF1）反馈的双稳态类型的逻辑电路链 -s）和逻辑门电路（OR1，OR2，OR3），并且通过将串行线路传送到所述链路中的逻辑电路的输入端子（S）的相应内部开关（TG1）连接到串行线路， 该串行线形成作为寄存器的输出元件的D型触发器（FFD）的输入。

    Input stage with dynamic hysteresis
    7.
    发明公开
    Input stage with dynamic hysteresis 审中-公开
    Eingangsstufe mit dynamischer滞后

    公开(公告)号：EP1071215A1

    公开(公告)日：2001-01-24

    申请号：EP99830457.0

    申请日：1999-07-19

    Applicant: STMicroelectronics S.r.l.

    Inventor： Fucili, Giona

    IPC: H03K19/00 ,  H03K19/017

    CPC classification number: H03K19/01721 ,  H03K19/0027

    Abstract: A circuit for shifting the triggering threshold of a stage (MP1,MN1) having an input coupled to a circuital node (OUT), following the sensing of a switching phase of said node from a logic state to another and for the remaining duration of the switching phase, produces a hysteresis effectively greater than the maximum theoretical limit of hysteresis admitted by the triggering threshold of the stage (MP1,MN1) coupled to said circuital node. The circuit comprises at least two switches, a first switch (MP2) connected in an electric path between said circuital node (OUT) and a supply rail (Vdd) and the second switch (MN2) connected in an electric path between said circuital node (OUT) and ground; at least a generator (P1,P2) of a single pulse of duration equal or longer than the duration of the rise time and of the fall time of the voltage on said circuital node, and shorter than the minimum time of persistence at a certain logic state of said circuital node (OUT), having an input coupled to said circuital node (OUT) and generating said single pulse upon sensing a switching from a logic state to another of said circuital node. Means coupled to an output of said pulse generator and to the control nodes of said switches configure the switches (MP2,MN2) in a state such to maintain the new logic state assumed by said circuital node (OUT) for the duration of said single pulse.

    Abstract translation: 一种用于将具有耦合到电路节点（OUT）的输入的级（MP1，MN1）的触发阈值移位的电路，在将所述节点的切换阶段从逻辑状态检测到另一状态之后， 开关相位产生滞后有效地大于耦合到所述电路节点的级（MP1，MN1）的触发阈值允许的滞后的最大理论极限。 该电路包括至少两个开关，连接在所述电路节点（OUT）和电源轨（Vdd）之间的电气路径中的第一开关（MP2）和第二开关（MN2），该第二开关连接在所述电路节点 OUT）和地面; 至少一个持续时间等于或长于上升时间的持续时间的单个脉冲的发生器（P1，P2）和所述电路节点上的电压的下降时间，并且短于在某个逻辑处的持续时间的最小时间 所述电路节点（OUT）的状态具有耦合到所述电路节点（OUT）的输入并且在感测到从逻辑状态到所述电路节点的另一个的切换时产生所述单个脉冲。 耦合到所述脉冲发生器的输出和所述开关的控制节点的装置将开关（MP2，MN2）配置成在所述单个脉冲的持续时间期间保持由所述电路节点（OUT）假设的新的逻辑状态的状态 。

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