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    Voltage regulating circuit for a capacitive load
    1.
    发明公开
    Voltage regulating circuit for a capacitive load 有权
    Spannungsreglerfüreine kapazitive最后

    公开(公告)号：EP1065580A1

    公开(公告)日：2001-01-03

    申请号：EP99830418.2

    申请日：1999-06-30

    Applicant: STMicroelectronics S.r.l.

    Inventor： Khouri, Osama ,  Micheloni, Rino ,  Motta, Ilaria ,  Torelli, Guido

    IPC: G05F3/02 ,  G05F1/56 ,  G05F3/26 ,  H02J7/16

    CPC classification number: G05F3/242

    Abstract: A voltage regulating circuit for a capacitive load, being connected between first and second terminals of a supply voltage generator (VDD,GND) and having an input terminal (IN) and an output terminal (OUT), comprises an operational amplifier (OP) having an inverting (-) input terminal connected to the input terminal (IN) of the regulating circuit and a non-inverting (+) input terminal connected to an intermediate node of a voltage divider (R1,R2) which is connected between an output node connected to the output terminal (OUT) of the regulating circuit and the second terminal (GND) of the supply voltage generator, and having an output terminal connected, for driving a first field-effect transistor (MPU), between the output node and the first terminal (VDD) of the supply voltage generator, the output terminal of the operational amplifier being further connected to the output node through a compensation network (COMP), and comprises a second field-effect transistor (MPD1) connected between the output node and the second terminal of the supply voltage generator (GND) and having its gate terminal connected to a constant voltage generating circuit means (RB,CB,MB,IB).

    Abstract translation: 一种用于电容性负载的电压调节电路，连接在电源电压发生器（VDD，GND）的第一和第二端子之间并具有输入端（IN）和输出端（OUT），包括运算放大器（OP），其具有 连接到调节电路的输入端子（IN）的反相（ - ）输入端子和连接到分压器（R1，R2）的中间节点的非反相（+）输入端子，其连接在输出节点 连接到调节电路的输出端子（OUT）和电源电压发生器的第二端子（GND），并且具有用于驱动第一场效应晶体管（MPU）的输出端子连接在输出节点和 电源电压发生器的第一端子（VDD），运算放大器的输出端子通过补偿网络（COMP）进一步连接到输出节点，并且包括一个与之相连的第二场效应晶体管（MPD1） 在电源电压发生器（GND）的输出节点和第二端子上，并且其栅极端子连接到恒定电压发生电路装置（RB，CB，MB，IB）。

    Voltage boost device for nonvolatile memories, operating in a low consumption standby condition
    3.
    发明公开
    Voltage boost device for nonvolatile memories, operating in a low consumption standby condition 有权
    SpannungserhöherfürnichtflüchtigeSpeicher zum Betrieb im verbrauchsarmen Bereitschaftszustand

    公开(公告)号：EP1113450A1

    公开(公告)日：2001-07-04

    申请号：EP99830825.8

    申请日：1999-12-30

    Applicant: STMicroelectronics S.r.l.

    Inventor： Zammattio, Matteo ,  Motta, Ilaria ,  Micheloni, Rino ,  Golla, Carla

    IPC: G11C16/30 ,  G11C5/14

    CPC classification number: G11C16/30 ,  G11C5/145

    Abstract: A voltage boost device includes a first boost stage (4) and a second boost stage (5) connected to an input terminal and to an output terminal (10), the output terminal (10) supplying an output voltage higher than a supply voltage. The input terminal receives an operating condition signal (SB) having a first logic level representative of a standby operating state and a second logic level representative of an active operation state. The first boost stage (4) is enabled in presence of the second logic level of the operating condition signal (SB), and is disabled in presence of the first logic level of the operating condition signal (SB); the second boost stage (5) is controlled in a first operating condition in presence of the first logic level of the operating condition signal (SB), and is controlled in a second operating condition in presence of the second logic level of the operating condition signal (SB).

    Abstract translation: 升压装置包括连接到输入端和输出端（10）的第一升压级（4）和第二升压级（5），输出端（10）提供高于电源电压的输出电压。 输入端接收具有代表待机运行状态的第一逻辑电平的运行状态信号（SB）和表示主动运行状态的第二逻辑电平。 第一升压级（4）在存在操作条件信号（SB）的第二逻辑电平的情况下使能，并且在存在操作条件信号（SB）的第一逻辑电平的情况下被禁止; 在操作条件信号（SB）的第一逻辑电平存在的情况下，第二升压级（5）被控制在第一操作状态中，并且在操作状态信号的第二逻辑电平存在的情况下被控制在第二操作状态 （SB）。

    NAND flash memory device with compacted cell threshold voltage distribution
    6.
    发明公开
    NAND flash memory device with compacted cell threshold voltage distribution 审中-公开
    NAND Flash Speicher mit komprimierter Verteilung der Schwellspannungen der Speicherzellen

    公开(公告)号：EP1729306A1

    公开(公告)日：2006-12-06

    申请号：EP05104742.1

    申请日：2005-06-01

    Applicant: STMicroelectronics S.r.l.

    Inventor： Micheloni, Rino ,  Ravasio, Roberto ,  Motta, Ilaria

    IPC: G11C16/34

    CPC classification number: G11C16/3404 ,  G11C16/3409

    Abstract: A flash memory device with NAND architecture (100) is proposed. The memory device includes a matrix of memory cells (110) each one having a programmable threshold voltage, wherein the matrix includes at least one sector individually erasable (115) and it is arranged in a plurality of rows and columns with the cells of each row connected to the corresponding word line (WL) and the cells of each column arranged in a plurality of strings (125) of cells connected in series, the strings of each column being connected to a corresponding bit line (BL), wherein the memory device further includes means (320) for erasing the cells of a selected sector, and means (330) for restoring the threshold voltage of the erased cells, wherein the means for restoring acts in succession on each of a plurality of blocks of the sector, for each one of a set of selected bit lines the block including a group of cells connected to a set of selected word lines, the means for restoring including means (446a, 446b) for reading each group with respect to a limit value exceeding a reading reference value, means (451a, 451b) for programming only each group wherein the threshold voltage of at least one group does not reach said limit value, and means (449a, 449b) for stopping the restoring in response to the reaching of the limit value by at least one sub-set of the groups.

    Abstract translation: 提出了具有NAND架构（100）的闪存器件。 存储器件包括每个具有可编程阈值电压的存储器单元（110）的矩阵，其中该矩阵包括至少一个可单独地擦除的扇区（115），并且它被布置成多个行和列，每行的单元格 连接到相应的字线（WL）和排列成串联连接的多个单元串（125）的每列的单元，每列的串连接到对应的位线（BL），其中存储器件 还包括用于擦除所选扇区的单元的装置（320），以及用于恢复已擦除单元的阈值电压的装置（330），其中用于恢复的装置依次在该扇区的多个块中的每个块上作用， 一组选定位线中的每一个，包括连接到一组所选字线的一组单元的单元，所述恢复装置包括用于相对于超过一个限制值的每个组读取每个组的装置（446a，446b） 读取参考值，用于仅编程至少一个组的阈值电压未达到所述极限值的每个组的装置（451a，451b）以及用于响应于达到极限而停止恢复的装置（449a，449b） 至少一个组的子集的值。

    Method of regulating the voltages on the drain and body terminals of a nonvolatile memory cell during programming and corresponding programming circuit
    9.
    发明公开
    Method of regulating the voltages on the drain and body terminals of a nonvolatile memory cell during programming and corresponding programming circuit 审中-公开
    用于控制所述漏极的电压和一个非易失性存储器单元的编程时的基板和相应的编程电路的方法

    公开(公告)号：EP1331645A2

    公开(公告)日：2003-07-30

    申请号：EP02029092.0

    申请日：2002-12-30

    Applicant: STMicroelectronics S.r.l.

    Inventor： Micheloni, Rino ,  Mognoni, Sabina ,  Motta, Ilaria ,  Sacco, Andrea

    IPC: G11C16/30

    CPC classification number: G11C16/30

    Abstract: The invention relates to a method and a programming circuit for the regulation of voltages on the drain (D) and body (B) terminals of a non-volatile memory cell (3) while being programmed. These voltages are applied through a programming circuit (1) inserted on a conduction pattern that transfers a predetermined voltage value (VPD,Vb) on at least one terminal (D,B) of the memory cell. The method comprises a local regulation phase of said voltage value, within the programming circuit, for deleting the effect of a parasitic resistor (R par ) lying on the conduction pattern.

    Abstract translation: 本发明涉及一种方法和一种编程电路，用于电压在漏极（D）和体（B）的调节中的非易失性存储单元（3）而被编程的端子。 （1）插入这些电压通过一个编程电路施加在传导图案做传输预定的电压值（VPD，Vb）中的至少一个端子上（D，B）的存储单元的。 该方法包括将所述电压值的本地调节阶段，编程电路内，用于删除一个寄生电阻器（R PAR）的影响躺在传导图案。

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