公开(公告)号：EP1713119A2

公开(公告)日：2006-10-18

申请号：EP06007580.1

申请日：2006-04-11

Applicant: STMicroelectronics S.r.l.

Inventor： Fazio, Giuseppe ,  Spandre, Alessandro ,  Petruzza, Pietro

IPC: H01L21/311 ,  H01L21/66

CPC classification number: H01J37/32972 ,  H01J37/32935 ,  H01L21/31116

Abstract: The present invention relates to a method for patterning a film of silicon nitride (14) landing over a silicon oxide substrate (12) for the manufacture of an integrated circuit. The method comprises the steps of:
- etching at least one portion of a silicon nitride (14) surface with plasma (15) containing Cl 2 , BCl 3 and CHF 3 , whereby performing an etching reaction to define tapered trenches within the silicon nitride (14), wherein the plasma further comprises an inert gas which is indifferent in the etching reaction,
- monitoring an infrared frequency emission signal (16) resulting from etching reaction products;
- correlating a variation of the infrared frequency emission signal (16) with an etching across an interface area between the silicon nitride (14) and the silicon oxide substrate (12).

Abstract translation: 本发明涉及一种用于图案化氮化硅膜（14）的方法，该氮化硅层叠在氧化硅衬底（12）上，用于制造集成电路。 该方法包括以下步骤： - 用包含Cl 2，BCl 3和CHF 3的等离子体（15）蚀刻氮化硅（14）表面的至少一部分，由此进行蚀刻反应以限定氮化硅内的锥形沟槽（ 14），其中所述等离子体还包括在所述蚀刻反应中无差异的惰性气体， - 监测由蚀刻反应产物产生的红外频率发射信号（16）; - 将红外线发射信号（16）的变化与氮化硅（14）和氧化硅衬底（12）之间的界面区域的蚀刻相关联。

公开(公告)号：EP1713119A3

公开(公告)日：2006-11-08

申请号：EP06007580.1

申请日：2006-04-11

Applicant: STMicroelectronics S.r.l.

Inventor： Fazio, Giuseppe ,  Spandre, Alessandro ,  Petruzza, Pietro

IPC: H01L21/311 ,  H01L21/66 ,  H01J37/32

CPC classification number: H01J37/32972 ,  H01J37/32935 ,  H01L21/31116

Abstract: The present invention relates to a method for patterning a film of silicon nitride (14) landing over a silicon oxide substrate (12) for the manufacture of an integrated circuit. The method comprises the steps of:
- etching at least one portion of a silicon nitride (14) surface with plasma (15) containing Cl 2 , BCl 3 and CHF 3 , whereby performing an etching reaction to define tapered trenches within the silicon nitride (14), wherein the plasma further comprises an inert gas which is indifferent in the etching reaction,
- monitoring an infrared frequency emission signal (16) resulting from etching reaction products;
- correlating a variation of the infrared frequency emission signal (16) with an etching across an interface area between the silicon nitride (14) and the silicon oxide substrate (12).

公开(公告)号：EP1475848B1

公开(公告)日：2006-12-20

申请号：EP03425293.2

申请日：2003-05-07

Applicant: STMicroelectronics S.r.l. ,  Ovonyx Inc.

Inventor： Spandre, Alessandro

IPC: H01L45/00 ,  H01L21/467

CPC classification number: H01L45/1233 ,  C23F4/00 ,  H01L45/06 ,  H01L45/144 ,  H01L45/1675

公开(公告)号：EP1557875A1

公开(公告)日：2005-07-27

申请号：EP03425827.7

申请日：2003-12-29

Applicant: STMicroelectronics S.r.l. ,  OVONYX Inc.

Inventor： Spandre, Alessandro

IPC: H01L21/311

CPC classification number: H01L21/31116 ,  H01L21/76804 ,  H01L27/2445 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1691

Abstract: A process for forming a tapered trench (31) in a dielectric material includes the steps of forming a dielectric layer (27) on a semiconductor wafer (10), and plasma etching the dielectric layer (27); during the plasma etch, the dielectric layer (27) is chemically and physically etched simultaneously.

Abstract translation: 一种用于在电介质材料上形成一锥形的沟槽（31）的过程包括：形成在半导体晶片（10）上的介电层（27），和等离子蚀刻所述介电层（27）的步骤; 等离子体蚀刻过程中，介电层（27）是化学和物理上同时蚀刻。

公开(公告)号：EP1475848A1

公开(公告)日：2004-11-10

申请号：EP03425293.2

申请日：2003-05-07

Applicant: STMicroelectronics S.r.l. ,  OVONYX Inc.

Inventor： Spandre, Alessandro

IPC: H01L45/00 ,  H01L21/467

CPC classification number: H01L45/1233 ,  C23F4/00 ,  H01L45/06 ,  H01L45/144 ,  H01L45/1675

Abstract: A process for defining a chalcogenide material layer (13) using a chlorine based plasma and a mask (30), wherein the portions of the chalcogenide material layer that are not covered by the mask are etched away. In a phase change memory cell having a stack (10) of a chalcogenide material layer (13) and an AlCu layer (17), the AlCu layer (17) is etched first using a chlorine based plasma at a higher temperature; then the lateral walls of the AlCu layer (17) are passivated (40); and then the chalcogenide material layer (13) is etched at a lower temperature.

Abstract translation: 的方法，用于限定使用氯等离子体和掩模（30）worin硫属化物材料层的部分并没有被掩模覆盖的硫属化物材料层（13）被蚀刻掉。 在具有硫族化物材料层（13）的堆叠（10）的相变存储单元，并在铝铜层（17），该铝铜层（17）首先使用蚀刻在较高温度下为氯基等离子体; 然后铝铜层（17）的侧壁被钝化（40）; 然后与硫属化物材料层（13）在较低温度下进行蚀刻。