公开(公告)号：EP1713119A2

公开(公告)日：2006-10-18

申请号：EP06007580.1

申请日：2006-04-11

Applicant: STMicroelectronics S.r.l.

Inventor： Fazio, Giuseppe ,  Spandre, Alessandro ,  Petruzza, Pietro

IPC: H01L21/311 ,  H01L21/66

CPC classification number: H01J37/32972 ,  H01J37/32935 ,  H01L21/31116

Abstract: The present invention relates to a method for patterning a film of silicon nitride (14) landing over a silicon oxide substrate (12) for the manufacture of an integrated circuit. The method comprises the steps of:
- etching at least one portion of a silicon nitride (14) surface with plasma (15) containing Cl 2 , BCl 3 and CHF 3 , whereby performing an etching reaction to define tapered trenches within the silicon nitride (14), wherein the plasma further comprises an inert gas which is indifferent in the etching reaction,
- monitoring an infrared frequency emission signal (16) resulting from etching reaction products;
- correlating a variation of the infrared frequency emission signal (16) with an etching across an interface area between the silicon nitride (14) and the silicon oxide substrate (12).

Abstract translation: 本发明涉及一种用于图案化氮化硅膜（14）的方法，该氮化硅层叠在氧化硅衬底（12）上，用于制造集成电路。 该方法包括以下步骤： - 用包含Cl 2，BCl 3和CHF 3的等离子体（15）蚀刻氮化硅（14）表面的至少一部分，由此进行蚀刻反应以限定氮化硅内的锥形沟槽（ 14），其中所述等离子体还包括在所述蚀刻反应中无差异的惰性气体， - 监测由蚀刻反应产物产生的红外频率发射信号（16）; - 将红外线发射信号（16）的变化与氮化硅（14）和氧化硅衬底（12）之间的界面区域的蚀刻相关联。

公开(公告)号：EP1713119A3

公开(公告)日：2006-11-08

申请号：EP06007580.1

申请日：2006-04-11

Applicant: STMicroelectronics S.r.l.

Inventor： Fazio, Giuseppe ,  Spandre, Alessandro ,  Petruzza, Pietro

IPC: H01L21/311 ,  H01L21/66 ,  H01J37/32

CPC classification number: H01J37/32972 ,  H01J37/32935 ,  H01L21/31116

Abstract: The present invention relates to a method for patterning a film of silicon nitride (14) landing over a silicon oxide substrate (12) for the manufacture of an integrated circuit. The method comprises the steps of:
- etching at least one portion of a silicon nitride (14) surface with plasma (15) containing Cl 2 , BCl 3 and CHF 3 , whereby performing an etching reaction to define tapered trenches within the silicon nitride (14), wherein the plasma further comprises an inert gas which is indifferent in the etching reaction,
- monitoring an infrared frequency emission signal (16) resulting from etching reaction products;
- correlating a variation of the infrared frequency emission signal (16) with an etching across an interface area between the silicon nitride (14) and the silicon oxide substrate (12).

公开(公告)号：EP1729355A1

公开(公告)日：2006-12-06

申请号：EP05104879.1

申请日：2005-06-03

Applicant: STMicroelectronics S.r.l.

Inventor： Pellizzer, Fabio ,  Bez, Roberto ,  Varesi, Enrico ,  Pirovano, Agostino ,  Petruzza, Pietro

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/06 ,  H01L27/2445 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1691

Abstract: A process for manufacturing phase change memory cells includes the step of forming a heater element (25a) in a semiconductor wafer (10) and a storage region (31a) of a phase change material on and in contact with the heater element (25a). In order to form the heater element (25a) and the phase change storage region (31a) a heater structure is first formed and a phase change layer (31) is deposited on and in contact with the heater structure. Then, the phase change layer (31) and the heater structure are defined by subsequent self-aligned etch steps.

Abstract translation: 用于制造相变存储单元的方法包括在半导体晶片（10）中形成加热元件（25a）和在与加热器元件（25a）接触并与之接触的相变材料的存储区域（31a）的步骤。 为了形成加热器元件（25a）和相变储存区域（31a），首先形成加热器结构，并且相变层（31）沉积在加热器结构上并与加热器结构接触。 然后，通过随后的自对准蚀刻步骤限定相变层（31）和加热器结构。

公开(公告)号：EP1729355B1

公开(公告)日：2008-11-19

申请号：EP05104879.1

申请日：2005-06-03

Applicant: STMicroelectronics S.r.l.

Inventor： Pellizzer, Fabio ,  Bez, Roberto ,  Varesi, Enrico ,  Pirovano, Agostino ,  Petruzza, Pietro

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/06 ,  H01L27/2445 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1691

Abstract: A process for manufacturing phase change memory cells includes the step of forming a heater element (25a) in a semiconductor wafer (10) and a storage region (31a) of a phase change material on and in contact with the heater element (25a). In order to form the heater element (25a) and the phase change storage region (31a) a heater structure is first formed and a phase change layer (31) is deposited on and in contact with the heater structure. Then, the phase change layer (31) and the heater structure are defined by subsequent self-aligned etch steps.