公开(公告)号：EP4033603A1

公开(公告)日：2022-07-27

申请号：EP22151920.0

申请日：2022-01-18

Applicant: STMicroelectronics S.r.l.

Inventor： GRAZIOSI, Giovanni ,  SANNA, Aurora ,  VILLA, Riccardo

IPC: H01Q1/22 ,  H01Q9/32 ,  H01Q1/40

Abstract: An antenna-in-package (AiP) semiconductor device (10) comprises a semiconductor chip (14) coupled to a planar substrate (12) and a rectilinear wire antenna (100) extending along an antenna axis (X100) transverse to the planar substrate (12). The rectilinear wire antenna (100) is electrically coupled (12) to the semiconductor chip (14) and bonded to the planar substrate (12), thus projecting from the planar substrate (12).
A mass of encapsulation material (20) encapsulates the semiconductor chip (14) coupled to the planar substrate (12) with a cavity (100A) formed in the mass of encapsulation material (20) extending to the planar substrate (12) along the antenna axis (X100).
The rectilinear wire antenna (100) is bonded to the planar substrate (12) at the bottom of the at least one cavity (100A) and thus extends in the cavity (100A) formed (LB) in the mass of encapsulation material (20).

公开(公告)号：EP4113600A1

公开(公告)日：2023-01-04

申请号：EP22181327.2

申请日：2022-06-27

Applicant: STMicroelectronics S.r.l.

Inventor： VILLA, Riccardo ,  DE SANTA, Matteo

IPC: H01L23/495 ,  H01L23/498

Abstract: One or more semiconductor chips are arranged over a substrate such as a leadframe (12) and a plurality of current-carrying formations such as ribbons (16A, 16B, 16C) are coupled to the semiconductor chip(s) with the substrate (12) exempt from electrically conductive formations coupling the ribbons.
Electrical contacts (162) such as electrical contacts are formed via wedge bonding, for instance, between adjacent current ribbons (16A, 16B) so that adjacent ribbons (16A, 16B) having a contact (162) formed therebetween are coupled into a multi-formation current-carrying channel (CH#1).

公开(公告)号：EP4273923A1

公开(公告)日：2023-11-08

申请号：EP23170386.9

申请日：2023-04-27

Applicant: STMicroelectronics S.r.l.

Inventor： VILLA, Riccardo

IPC: H01L23/433 ,  H01L23/495

Abstract: At least one semiconductor chip or die (14) is arranged on a first surface of a thermally conductive die pad (12A) in a substrate such as a leadframe. An encapsulation (20) of insulating material in molded onto the die pad (12A) having the semiconductor die (14) arranged on the first surface. At the second surface of the die pad (12A), opposite the first surface, the encapsulation (18) borders on the die pad (12A) at a borderline around the die pad (12A). A recessed portion (120A) of the encapsulation (18, 20) is provided, e.g., via laser ablation, at the borderline around the die pad (12A). Thermally and electrically conductive material such as metal material (122A) is filled in the recessed portion (120A) of the encapsulation (18, 20) around the die pad (12A). The thermally conductive die pad (12A) is augmented by the filling of thermally and electrically conductive material (122A) in the recessed portion (120A) of the encapsulation (18, 20) thus improving thermal performance of the device (10).