公开(公告)号：EP4033603A1

公开(公告)日：2022-07-27

申请号：EP22151920.0

申请日：2022-01-18

Applicant: STMicroelectronics S.r.l.

Inventor： GRAZIOSI, Giovanni ,  SANNA, Aurora ,  VILLA, Riccardo

IPC: H01Q1/22 ,  H01Q9/32 ,  H01Q1/40

Abstract: An antenna-in-package (AiP) semiconductor device (10) comprises a semiconductor chip (14) coupled to a planar substrate (12) and a rectilinear wire antenna (100) extending along an antenna axis (X100) transverse to the planar substrate (12). The rectilinear wire antenna (100) is electrically coupled (12) to the semiconductor chip (14) and bonded to the planar substrate (12), thus projecting from the planar substrate (12).
A mass of encapsulation material (20) encapsulates the semiconductor chip (14) coupled to the planar substrate (12) with a cavity (100A) formed in the mass of encapsulation material (20) extending to the planar substrate (12) along the antenna axis (X100).
The rectilinear wire antenna (100) is bonded to the planar substrate (12) at the bottom of the at least one cavity (100A) and thus extends in the cavity (100A) formed (LB) in the mass of encapsulation material (20).

公开(公告)号：EP3832716A1

公开(公告)日：2021-06-09

申请号：EP20210563.1

申请日：2020-11-30

Applicant: STMicroelectronics S.r.l.

Inventor： SOMMA, Cristina ,  GRAZIOSI, Giovanni

IPC: H01L23/498 ,  H01L23/50 ,  H01L23/538

Abstract: An assortment of semiconductor devices (10, 20) is designed by designing a first device (10), such as e.g. a mid/low-performance package, with a first rectangular substrate (11) having a first width (X) and a first length (Y) as well as a central semiconductor circuit mounting location (12) with electrically-conductive formations (a ball grid array or BGA, for instance) providing a first pattern of electrical interface nodes at first (10A), second (10B) and third (10C) sides of the rectangular shape as well as a first set (R1, R3) of electrical interface nodes at the fourth side (10D) of the rectangular shape. A second semiconductor device (20), such as a high-performance package, for instance, is designed with a second rectangular shape having a second width (X') equal to the first width (X), a second length (Y') and a median line (ML) extending in the direction of the second width (X') as well as a pair of semiconductor circuit mounting locations (221, 222) on opposite sides of the median line (ML). A second pattern of electrical interface nodes for the second device (20) is designed to comprise two unmorphed replicas of the first pattern arranged mutually rotated 180° on opposite sides of the median line (ML) as well as two second sets (R2, R4) of electrical interface nodes located between the pair of semiconductor circuit mounting locations (221, 222) and comprising two smaller morphed replicas (R2, R4) of the first set (R1, R3) of electrical interface nodes arranged mutually rotated 180° on opposite sides of said median line, wherein the length (Y') of the second device (20) is less than twice the length (Y) of the first device (10).