公开(公告)号：EP1936627A1

公开(公告)日：2008-06-25

申请号：EP07123373.8

申请日：2007-12-17

Applicant: STMicroelectronics S.r.l.

Inventor： Torelli, Cosimo ,  Rimondi, Danilo ,  Zappa, Rita

IPC: G11C5/14 ,  G11C11/412 ,  G11C11/413

CPC classification number: G11C5/14 ,  G11C11/417

Abstract: A monolithically integrated electronic system having a plurality of operating modes and comprising distinct random access static storage resources, acess to which is differently contemplated for different modes of operation, and means for interrupting power supply to distinct static storage resources that are not utilized in the currently selected operating mode, has two or more distinct static storage resources defined in distinct sectors of a single array of memory cells, each of which is separately powered through a dedicated supply line/source. All sectors share a single peripheral address and write/read circuitry that is also powered through a distinct supply line/source.
The on or off state of distinct sectors is determined via software and commanded by the running program of a certain application by the integrated electronic system.
A sector contemplated to remain always powered is composed by memory cells having a higher threshold of that of the memory cells of the other sectors of the array to be programmably switched off.

Abstract translation: 一种单片集成电子系统，其具有的操作模式的多元性和包含不同的随机接入的静态存储资源，接取所有被不同地预期用于不同的操作模式的装置，以及用于中断到确实未在当前使用的不同的静态存储资源电源 选择的操作模式，在存储器单元的单个阵列的不同扇区定义的两个或多个不同的静态存储资源，每一个的全部，其分别通过专用的供给线/电源供电。 所有扇区共享一个外设地址和读/写电路都IST通过不同的供应线/电源供电。 由集成电子系统通过软件的打开或关闭不同扇区的状态被确定的开采和由特定应用程序的运行的程序命令的。考虑到保持始终通电由具有做的存储器单元中的一个较高的阈值的存储单元构成的扇区 阵列的其他扇区被可编程地关闭。

公开(公告)号：EP1624465A1

公开(公告)日：2006-02-08

申请号：EP04425617.0

申请日：2004-08-06

Applicant: STMicroelectronics S.r.l.

Inventor： Zappa, Rita ,  Selva, Carolina ,  Rimondi, Danilo ,  Torelli, Cosimo

IPC: G11C29/00

CPC classification number: G11C29/16 ,  G11C29/44 ,  G11C29/4401 ,  G11C29/72

Abstract: A built-in self-test and self-repair structure (BISR) of memory arrays embedded in an integrated device, including at least a test block (BIST) programmable to execute on a respective memory array of the device any of a certain number of predefined test algorithms, and a self-repair block that includes a column address generator processing the faulty addresses information for allocating redundant resources of the tested memory array, a redundancy register on which final redundancy information are loaded at each power-on of the device and a control logic for managing data transfer from external circuitry to the built-in self-test and self-repair structure (BISR) and vice versa, utilizes a single built-in self-test (BIST) structure serves any number of embedded memory arrays even of different type and size.
The built-in self-test and self-repair (BISR) structure further includes nonvolatile storage means containing information on addresses and data bus sizes of the device architecture, aspect ratio, capacity, multiplexing and scrambling parameters and relative test algorithm instructions for each of said embedded memory arrays and on which redundance column addresses are permanently stored and a multiple frequency clock generator for selecting the maximum operating clock frequency of the type of embedded memory array to be accessed.
Two distinct selectable test flows of an embedded random access memory array are selectable by programming. A first two-step test flow, each step of which includes the execution of a complete BIST check on the array, and a second three-step test flow, each step of which includes the execution of a complete BIST check on the array, the third BIST check revealing a possible failed programming of the redundance column addresses in said nonvolatile storage means.

Abstract translation: 甲内建自测试，并在集成设备中的嵌入式存储器阵列中的自修复结构（BISR），包括至少一个测试块（BIST）可编程的，以执行设备的任何特定数量的的respectivement存储器阵列 预定义的测试算法和一个自修复块做了包括上电设备的列地址发生器处理，以分配测试存储器阵列，其上最终冗余信息在每个加载的冗余寄存器的冗余资源的故障地址的信息和 用于管理从外部电路的数据传送到控制逻辑内置自测试和自修复结构（BISR），反之亦然，利用单个内建自测试（BIST）结构用于任何数目的嵌入式存储器阵列的 甚至不同的类型和大小。 该内建自测试和自修复（BISR）结构还包括非易失性存储装置，包含对每个的地址和设备架构的数据总线大小，长宽比，容量，复用和扰频参数和相对测试算法的指令信息 所述嵌入的存储器阵列和在其冗余列地址永久地存储和被访问，用于选择嵌入式存储器阵列的类型的最大工作时钟频率的倍数的频率的时钟发生器。 嵌入式随机存取存储器阵列的两个不同的可选择的测试流是由编程选择。 第一两步测试流，每个步骤都包括在阵列上的完整BIST检查的执行，和一个第二三步测试流，每个步骤都包括一个完整的BIST检查阵列上执行，所述 第三BIST检查揭示在所述非易失性存储装置中的冗余列地址的一个可能的编程失败。

公开(公告)号：EP1624464A1

公开(公告)日：2006-02-08

申请号：EP04425613.9

申请日：2004-08-05

Applicant: STMicroelectronics S.r.l.

Inventor： Selva, Carolina ,  Zappa, Rita ,  Rimondi, Danilo ,  Torelli, Cosimo ,  Mastrodomenico, Giovanni

IPC: G11C29/00

CPC classification number: G11C29/44 ,  G11C29/16 ,  G11C29/56008 ,  G11C2029/1208 ,  G11C2029/1806 ,  G11C2029/3602

Abstract: A self diagnosis (BISD) device for a random memory array, preferably integrated with the random access memory, executes a certain number of predefined test algorithms and identifies addresses of faulty locations. The BISD device recognizes certain fail patterns of interest and generates bit-strings corresponding to them.
In practice, the BISD device diagnoses automatically memory arrays and allow to identify defects in the production process that affect a new technology during its learning phase, thus accelerating its "maturation".

Abstract translation: 用于随机存储器阵列的自诊断（BISD）装置优选地与随机存取存储器集成，执行一定数量的预定义的测试算法并识别故障位置的地址。 BISD设备识别感兴趣的某些故障模式并生成与它们相对应的位串。 在实践中，BISD设备自动诊断内存阵列，并允许在其学习阶段识别影响新技术的生产过程中的缺陷，从而加速其“成熟”。