公开(公告)号：EP1659637B1

公开(公告)日：2011-01-12

申请号：EP05025287.3

申请日：2005-11-18

Applicant: STMicroelectronics Srl

Inventor： Arena, Giuseppe ,  Ferla, Giuseppe ,  Camalleri, Marco

IPC: H01L29/78 ,  H01L29/423 ,  H01L21/336 ,  H01L21/28

CPC classification number: H01L29/7802 ,  H01L21/2815 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/4933 ,  H01L29/66712

Abstract: The invention relates to a process for the realisation of a high integration density power MOS device comprising the following steps of: providing a doped semiconductor substrate (10) with a first type of conductivity (N); forming, on the substrate (10), a semiconductor layer (11) with lower conductivity (N-); forming, on the semiconductor layer (11), a dielectric layer (16) of thickness comprised between 3000 and 13000 A (Angstrom); depositing, on the dielectric layer (16), a hard mask layer; masking the hard mask layer by means of a masking layer; etching the hard mask layers and the underlying dielectric layer (16) for defining a plurality of hard mask portions (19) to protect said dielectric layer (16); removing the masking layer; isotropically and laterally etching said dielectric layer forming lateral cavities in said dielectric layer (16) below said hard mask portions (19); forming a gate oxide (15) of thickness comprised between 150 and 1500 A (Angstrom) depositing a conductor material (24) in said cavities and above the same to form a recess spacer (20), which is totally aligned with a gate structure (14) comprising said thick dielectric layer (16) and said gate oxide (15).