公开(公告)号：EP1659637B1

公开(公告)日：2011-01-12

申请号：EP05025287.3

申请日：2005-11-18

Applicant: STMicroelectronics Srl

Inventor： Arena, Giuseppe ,  Ferla, Giuseppe ,  Camalleri, Marco

IPC: H01L29/78 ,  H01L29/423 ,  H01L21/336 ,  H01L21/28

CPC classification number: H01L29/7802 ,  H01L21/2815 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/4933 ,  H01L29/66712

Abstract: The invention relates to a process for the realisation of a high integration density power MOS device comprising the following steps of: providing a doped semiconductor substrate (10) with a first type of conductivity (N); forming, on the substrate (10), a semiconductor layer (11) with lower conductivity (N-); forming, on the semiconductor layer (11), a dielectric layer (16) of thickness comprised between 3000 and 13000 A (Angstrom); depositing, on the dielectric layer (16), a hard mask layer; masking the hard mask layer by means of a masking layer; etching the hard mask layers and the underlying dielectric layer (16) for defining a plurality of hard mask portions (19) to protect said dielectric layer (16); removing the masking layer; isotropically and laterally etching said dielectric layer forming lateral cavities in said dielectric layer (16) below said hard mask portions (19); forming a gate oxide (15) of thickness comprised between 150 and 1500 A (Angstrom) depositing a conductor material (24) in said cavities and above the same to form a recess spacer (20), which is totally aligned with a gate structure (14) comprising said thick dielectric layer (16) and said gate oxide (15).

公开(公告)号：EP1742257B1

公开(公告)日：2012-09-05

申请号：EP05425483.4

申请日：2005-07-08

Applicant: STMicroelectronics Srl

Inventor： Arena, Giuseppe ,  Donato, Caterina ,  Camalleri, Cateno Marco ,  Magri', Angelo

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/423 ,  H01L29/51 ,  H01L29/49 ,  H01L29/06 ,  H01L29/08

CPC classification number: H01L29/7813 ,  H01L29/0623 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/4933 ,  H01L29/511 ,  H01L29/66734

Abstract: A trench (5) is formed in a semiconductor body (2); the side walls and the bottom of the trench are covered with a first dielectric material layer (9); the trench (5) is filled with a second dielectric material layer (10); the first and the second dielectric material layers (9, 10) are etched via a partial, simultaneous and controlled etching such that the dielectric materials have similar etching rates; a gate-oxide layer (13) having a thickness smaller than the first dielectric material layer (9) is deposited on the walls of the trench (5); a gate region (14) of conductive material is formed within the trench (5); and body regions (7) and source regions (8) are formed within the semiconductor body (2), at the sides of and insulated from the gate region (14). Thereby, the gate region (14) extends only on top of the remaining portions of the first and second dielectric material layers (9, 10).