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    Method of manufacturing a power MOS device
    2.
    发明授权
    Method of manufacturing a power MOS device 有权
    一种用于制造MOS功率器件的工艺

    公开(公告)号：EP1659637B1

    公开(公告)日：2011-01-12

    申请号：EP05025287.3

    申请日：2005-11-18

    Applicant: STMicroelectronics Srl

    Inventor： Arena, Giuseppe ,  Ferla, Giuseppe ,  Camalleri, Marco

    IPC: H01L29/78 ,  H01L29/423 ,  H01L21/336 ,  H01L21/28

    CPC classification number: H01L29/7802 ,  H01L21/2815 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/4933 ,  H01L29/66712

    Abstract: The invention relates to a process for the realisation of a high integration density power MOS device comprising the following steps of: providing a doped semiconductor substrate (10) with a first type of conductivity (N); forming, on the substrate (10), a semiconductor layer (11) with lower conductivity (N-); forming, on the semiconductor layer (11), a dielectric layer (16) of thickness comprised between 3000 and 13000 A (Angstrom); depositing, on the dielectric layer (16), a hard mask layer; masking the hard mask layer by means of a masking layer; etching the hard mask layers and the underlying dielectric layer (16) for defining a plurality of hard mask portions (19) to protect said dielectric layer (16); removing the masking layer; isotropically and laterally etching said dielectric layer forming lateral cavities in said dielectric layer (16) below said hard mask portions (19); forming a gate oxide (15) of thickness comprised between 150 and 1500 A (Angstrom) depositing a conductor material (24) in said cavities and above the same to form a recess spacer (20), which is totally aligned with a gate structure (14) comprising said thick dielectric layer (16) and said gate oxide (15).

    Vertical power semiconductor device and method of making the same
    4.
    发明公开
    Vertical power semiconductor device and method of making the same 审中-公开
    垂直功率半导体器件及其制造方法

    公开(公告)号：EP2309545A2

    公开(公告)日：2011-04-13

    申请号：EP10015764.3

    申请日：2004-09-30

    Applicant: STMicroelectronics Srl

    Inventor： Frisina, Ferruccio ,  Ferla, Giuseppe ,  Magri', Angelo

    IPC: H01L29/78 ,  H01L29/417 ,  H01L29/08

    CPC classification number: H01L29/66666 ,  H01L21/26586 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/417 ,  H01L29/41708 ,  H01L29/41716 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/66128 ,  H01L29/66272 ,  H01L29/66333 ,  H01L29/66712 ,  H01L29/7322 ,  H01L29/7398 ,  H01L29/7809 ,  H01L29/8611

    Abstract: A vertical power semiconductor device and corresponding realisation method, the device being integrated on a semiconductor substrate (10) and comprising respective gate (20), source (25) and drain (30) areas, realised in an epitaxial layer (40) arranged on said semiconductor substrate (10) and comprising respective gate (21), source (26) and drain (31) metallisations realised by means of a first metallisation level as well as gate (60), source (65) and drain (70) terminals or pads realised by means of a second metallisation level. The device is configured as a set of modular areas (100) extending parallel to each other, each having a rectangular elongate source area (25) perimetrically surrounded by a narrow gate area (20), and separated from each other by regions (30a) with drain area (30) extending parallel and connected at the opposite ends thereof to a second closed region (30b) with drain area (30) forming a device outer peripheral edge; as well as a sinker structure (45) extending perpendicularly to the substrate and formed by a grid of sinker (S) located below both the first parallel regions (30a) and the second closed region (30b) with drain area (30) in order to favour a conductive channel for a current coming from the source area (25) and directed towards the drain area (30) across the substrate (10).

    Abstract translation: 一种垂直功率半导体器件及其相应的实现方法，所述器件集成在半导体衬底（10）上并且包括在外延层（40）中实现的相应的栅极（20），源极（25）和漏极（30）区域， 所述半导体衬底（10）包括相应的栅极（21），通过第一金属化层以及栅极（60），源极（65）和漏极（70）端子实现的源极（26）和漏极（31） 或通过第二金属化层实现的焊盘。 该装置被配置为一组彼此平行延伸的模块化区域（100），每个模块化区域具有由窄的栅极区域（20）沿周向环绕的矩形细长源区域（25），并且通过区域（30a）彼此分开， 其中漏极区域（30）平行地延伸并且在其相对端处连接到第二封闭区域（30b），其中漏极区域（30）形成装置外周边缘; 以及垂直于衬底延伸并且由位于第一平行区域（30a）下方的沉降片（S）网格和具有排出区域（30）的第二封闭区域（30b）依次形成的沉降片结构（45） 以支持用于来自源极区域（25）的电流的导电沟道，并跨过衬底（10）指向漏极区域（30）。

    Power MOS device and corresponding manufacturing method
    5.
    发明授权
    Power MOS device and corresponding manufacturing method 有权
    MOS功率器件和相应的制造方法

    公开(公告)号：EP1659638B1

    公开(公告)日：2011-01-12

    申请号：EP05025288.1

    申请日：2005-11-18

    Applicant: STMicroelectronics Srl

    Inventor： Magri', Angelo ,  Frisina, Ferruccio ,  Ferla, Giuseppe

    IPC: H01L29/78 ,  H01L29/423 ,  H01L21/336 ,  H01L29/49 ,  H01L21/28

    CPC classification number: H01L29/7802 ,  H01L21/2815 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66712

    Abstract: Power MOS device of the type comprising a plurality of elementary power MOS transistors (2) having respective gate structures (12) and comprising a gate oxide (7) with double thickness having a thick central part (8) and lateral portions (9) of reduced thickness. Such device exhibiting gate structures (12) comprising first gate conductive portions (13) overlapped onto said lateral portions (9) of reduced thickness to define, for the elementary Mos transistors (2), the gate electrodes, as well as a conductive structure or mesh (14). Such conductive structure (14) comprising a plurality of second conductive portions (15) overlapped onto the thick central part (8) of gate oxide (7) and interconnected to each other and to the first gate conductive portions (13) by means of a plurality of conducive bridges (16). The present invention further relates to a method for realising the power MOS device.

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