公开(公告)号：EP2390792B1

公开(公告)日：2014-04-16

申请号：EP11167701.9

申请日：2011-05-26

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics Srl

Inventor： Scandurra, Alberto ,  Guarnaccia, Giuseppe ,  Urzi', Ignazio Antonino

IPC: G06F13/42 ,  H04L12/00

CPC classification number: G06F13/42

公开(公告)号：EP2362318B1

公开(公告)日：2014-04-02

申请号：EP11153867.4

申请日：2011-02-09

Applicant: STMicroelectronics Srl ,  STMicroelectronics SA ,  STMicroelectronics (Grenoble 2) SAS

Inventor： Guarnaccia, Giuseppe ,  Guarrasi, Raffaele ,  Kacem, Radhia

IPC: G06F13/40 ,  G06F1/12 ,  G06F5/00 ,  H04L7/00

CPC classification number: G06F13/4059 ,  Y02D10/14 ,  Y02D10/151

Abstract: A synchronization system comprising a memory (12) and a control circuit (20). The control circuit (20) comprises: - a write interface for writing data in said memory (12) with a first clock signal, wherein the write interface is configured for operating with a write pointer in response to a write command, - a read interface for reading data from said memory (12) with a second clock signal, wherein the read interface is configured for operating with a read pointer in response to a read command, and - a synchronization circuit for synchronizing said write pointer and said read pointer with a synchronization latency. An elaboration circuit (30) is also provided for elaborating data in memory (12) with an elaboration latency, wherein the elaboration latency is smaller than the synchronization latency.

公开(公告)号：EP1995660B1

公开(公告)日：2013-07-10

申请号：EP07108878.5

申请日：2007-05-24

Applicant: STMicroelectronics Srl

Inventor： Mangano, Daniele ,  Scandurra, Alberto ,  Guarnaccia, Giuseppe

IPC: G06F5/06

CPC classification number: G06F13/4217