公开(公告)号：EP1710843B1

公开(公告)日：2012-09-19

申请号：EP05425194.7

申请日：2005-04-04

Applicant: STMicroelectronics Srl ,  STMicroelectronics S.A.

Inventor： Saggio, Mario Giuseppe ,  Longo Minnolo, Antonino ,  Germana', Rosalia

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/10 ,  H01L29/06

CPC classification number: H01L29/0634 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/1095 ,  H01L29/7803 ,  H01L29/7811

公开(公告)号：EP2290697B1

公开(公告)日：2016-07-06

申请号：EP10174803.6

申请日：2010-09-01

Applicant: STMicroelectronics Srl

Inventor： Saggio, Mario Giuseppe ,  Murabito, Domenico ,  Magrí, Angelo

IPC: H01L29/78 ,  H01L29/06 ,  H01L21/336 ,  H01L29/10 ,  H01L29/417

CPC classification number: H01L29/0634 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/086 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/66712 ,  H01L29/7395 ,  H01L29/7802 ,  H01L29/7811

Abstract: A high voltage semiconductor device comprising a semiconductor substrate (2) covered by an epitaxial layer (3) of a first type of conductivity having a plurality of column structures (4) comprising high aspect ratio deep trenches, said epitaxial layer (3) being covered by an active surface area (5), each of the column structures (4) comprising an external portion (6) formed by a silicon epitaxial layer of a second type of conductivity, and having a dopant charge which counterbalances the dopant charge in said epitaxial layer (3) outside said column structures (4), a dielectric filling portion (7) filling up said deep trench, and said external portion (6) having a dopant concentration with a variable concentration profile having a maximum near an interface with said epitaxial layer (3).

公开(公告)号：EP2299481A3

公开(公告)日：2011-05-18

申请号：EP10015719.7

申请日：2006-07-07

Applicant: STMicroelectronics Srl

Inventor： Saggio, Mario Giuseppe ,  Frisina, Ferruccio ,  Rascuna, Simone

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/7802 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/66712

Abstract: Process for manufacturing a multi-drain power electronic device (30) integrated on a semiconductor substrate (100) of a first type of conductivity whereon a drain semiconductor layer (20) is formed, characterised in that it comprises the following steps:
- forming at least a first semiconductor epitaxial layer (21) of the first type of conductivity of a first value of resistivity (ρ 1 ) forming the drain epitaxial layer (20) on the semiconductor substrate (100),
- forming in the first semiconductor layer (21) first sub-regions (51) of a second type of conductivity by means of a first selective implant step with a first implant dose (Φ 1P ),
- forming in the first semiconductor layer (21) second sub-regions (D1, D1a) of the first type of conductivity by means of a second implant step with a second implant dose (Φ 1N ),
- forming a surface semiconductor layer (23) wherein body regions (40) of the second type of conductivity are formed being aligned with the first sub-regions (51),
- carrying out a thermal diffusion process so that the first sub-regions (51) form a single electrically continuous column region (50) being aligned and in electric contact with the body regions (40).

公开(公告)号：EP1873837B1

公开(公告)日：2013-03-27

申请号：EP06425448.5

申请日：2006-06-28

Applicant: STMicroelectronics Srl

Inventor： Saggio, Mario Giuseppe ,  Murabito, Domenico ,  Frisina, Ferruccio

IPC: H01L29/06 ,  H01L29/861 ,  H01L29/78 ,  H01L21/329 ,  H01L21/336 ,  H01L29/417 ,  H01L29/08 ,  H01L21/20 ,  H01L21/324 ,  H01L29/739 ,  H01L29/872 ,  H01L29/732

CPC classification number: H01L29/7811 ,  H01L21/324 ,  H01L29/0615 ,  H01L29/0634 ,  H01L29/0661 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/41766 ,  H01L29/66128 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/73 ,  H01L29/7396 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7813 ,  H01L29/8611 ,  H01L29/872

Abstract: A process for manufacturing a semiconductor power device envisages the steps of: providing a body (3) made of semiconductor material having a first top surface (3a); forming an active region (4a; 29, 30) with a first type of conductivity in the proximity of the first top surface (3a) and inside an active portion (1a) of the body (3); and forming an edge-termination structure (4b, 5). The edge-termination structure is formed by: a ring region (5) having the first type of conductivity and a first doping level, set within a peripheral edge portion (1b) of the body (3) and electrically connected to the active region; and a guard region (4b), having the first type of conductivity and a second doping level, higher than the first doping level, set in the proximity of the first top surface (3a) and connecting the active region (4a; 29, 30) to the ring region (5). The process further envisages the steps of: forming a surface layer (9) having the first type of conductivity on the first top surface (3a), also at the peripheral edge portion (1b), in contact with the guard region; and etching the surface layer (9) in order to remove it above the edge portion (1b) in such a manner that the etch terminates inside the guard region (4b).

公开(公告)号：EP1710843A1

公开(公告)日：2006-10-11

申请号：EP05425194.7

申请日：2005-04-04

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics S.A.

Inventor： Saggio, Mario Giuseppe ,  Longo Minnolo, Antonino ,  Germana', Rosalia

IPC: H01L29/78 ,  H01L27/088

CPC classification number: H01L29/0634 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/1095 ,  H01L29/7803 ,  H01L29/7811

Abstract: The integrated power device comprises a semiconductor body (41, 42) of a first conductivity type comprising a first region (43) accommodating a start-up structure (14), and a second region (44) accommodating a power structure (18). The two structures (14, 18) are separated from one another by an edge structure (30) and are arranged in a mirror configuration with respect to a symmetry line of the edge structure (30). Both the start-up structure (14) and the power structure (18) are obtained using MOSFET devices. More in particular, both MOSFET devices are multi-drain MOSFET devices, having mesh regions (46, 47), source regions (50, 51) and gate regions (60, 61) separated from one another. In addition, both MOSFET devices have drain regions (42a, 42b) delimited by columns (52, 53) that repeat periodically at a fixed distance. Between the two MOSFET devices there is an electrical insulation of at least 25 V.

Abstract translation: 集成功率器件包括第一导电类型的半导体本体（41,42），包括容纳起动结构（14）的第一区域（43）和容纳功率结构（18）的第二区域（44）。 两个结构（14,18）通过边缘结构（30）彼此分离，并且相对于边缘结构（30）的对称线布置成镜子结构。 使用MOSFET器件获得启动结构（14）和功率结构（18）。 更具体地，两个MOSFET器件都是具有网格区域（46,47），源极区域（50,51）和彼此分离的栅极区域（60,61）的多漏极MOSFET器件。 此外，两个MOSFET器件具有由以固定距离周期性重复的列（52,53）限定的漏极区域（42a，42b）。 在两个MOSFET器件之间存在至少25V的电绝缘。