公开(公告)号：EP0110625B1

公开(公告)日：1989-09-20

申请号：EP83307009.7

申请日：1983-11-16

Applicant: STORAGE TECHNOLOGY CORPORATION

Inventor： Fitzpatrick, William B.

IPC: G11B5/09

CPC classification number: G11B20/1426

公开(公告)号：EP0110625A3

公开(公告)日：1985-09-11

申请号：EP83307009

申请日：1983-11-16

Applicant: STORAGE TECHNOLOGY CORPORATION

Inventor： Fitzpatrick, William B.

IPC: G11B05/09 ,  H04L25/49

CPC classification number: G11B20/1426

Abstract: Data pulses (DATA) are encoded in accordance with a 2,7 run length limited code by a simplified circuit comprising three cascaded flip-flops (33, 34, 35) clocking through the data pulses to provide signals A, B and C and two flip-flops (36, 37) clocking through an intermediate signal Y to provide signals D and E. The signal Y is provided by first NAND gates (40) in accordance with the equation Y = ACDE + BD. The encoded signal X is produced by second NAND gates (41) responsive not only to selected flip-flop outputs but to complementary clock signals (-ESR CLOCK, +ESR CLOCK), in accordance with the equation X = (+ESR GLOCK) . (BD) + (-ESR CLOCK) . (BCE + ABE).

公开(公告)号：EP0110625A2

公开(公告)日：1984-06-13

申请号：EP83307009.7

申请日：1983-11-16

Applicant: STORAGE TECHNOLOGY CORPORATION

Inventor： Fitzpatrick, William B.

IPC: G11B5/09

CPC classification number: G11B20/1426

Abstract: Data pulses (DATA) are encoded in accordance with a 2,7 run length limited code by a simplified circuit comprising three cascaded flip-flops (33, 34, 35) clocking through the data pulses to provide signals A, B and C and two flip-flops (36, 37) clocking through an intermediate signal Y to provide signals D and E. The signal Y is provided by first NAND gates (40) in accordance with the equation Y = ACDE + BD. The encoded signal X is produced by second NAND gates (41) responsive not only to selected flip-flop outputs but to complementary clock signals (-ESR CLOCK, +ESR CLOCK), in accordance with the equation X = (+ESR GLOCK) . (BD) + (-ESR CLOCK) . (BCE + ABE).

Abstract translation: 数据脉冲（DATA）根据2,7游程长度限制码通过包括三个级联触发器（33,34,35）的简化电路进行编码，该触发器通过数据脉冲计时以提供信号A，B和C以及两个 触发器（36,37）通过中间信号Y计时以提供信号D和E.信号Y根据等式Y = ACDE + BD由第一NAND门（40）提供。 根据等式X =（+ ESR GLOCK），编码信号X不仅响应于所选择的触发器输出而且响应于互补时钟信号（-ESR CLOCK，+ ESR CLOCK）而由第二NAND门（41）产生。 （BD）+（-ESR CLOCK）（BCE + ABE）。