GATE-CONTROLLED CHARGE MODULATED DEVICE FOR CMOS IMAGE SENSORS

    公开(公告)号:EP3528288A1

    公开(公告)日:2019-08-21

    申请号:EP18214935.1

    申请日:2014-06-20

    Applicant: Stratio, Inc.

    Abstract: A device for sensing light includes a first semiconductor region doped with a dopant of a first type and a second semiconductor region doped with a dopant of a second type. The second semiconductor region is positioned above the first semiconductor region. The device includes a gate insulation layer; a gate, a source, and a drain. The second semiconductor region has a top surface that is positioned toward the gate insulation layer and a bottom surface that is positioned opposite to the top surface of the second semiconductor region. The second semiconductor region has an upper portion that includes the top surface of the second semiconductor region and a lower portion that includes the bottom surface of the second semiconductor region and is mutually exclusive with the upper portion. The first semiconductor region is in contact with both the upper portion and the lower portion of the second semiconductor region.

    PEER-TO-PEER COMMUNICATION BASED ON DEVICE IDENTIFIERS
    3.
    发明申请
    PEER-TO-PEER COMMUNICATION BASED ON DEVICE IDENTIFIERS 审中-公开
    基于设备标识符的对等通信

    公开(公告)号:WO2016049558A1

    公开(公告)日:2016-03-31

    申请号:PCT/US2015/052410

    申请日:2015-09-25

    CPC classification number: H04L63/0876 G06F21/44 H04L63/104 H04W12/06 H04W12/08

    Abstract: A server system receives from a first electronic device a first device identifier and network information of the first electronic device; subsequent to receiving the first device identifier and the network information of the first electronic device, receives from a second electronic device a second device identifier and network information of the second electronic device; in response to receiving from the second electronic device the second device identifier and the network information of the second electronic device, determines whether the first device identifier is associated with the second device identifier; and, in accordance with a determination that the first device identifier is associated with the second device identifier, sends to the second electronic device the network information of the first electronic device and/or sends to the first electronic device the network information of the second electronic device.

    Abstract translation: 服务器系统从第一电子设备接收第一设备标识符和第一电子设备的网络信息; 在接收到第一设备标识符和第一电子设备的网络信息之后,从第二电子设备接收第二设备标识符和第二电子设备的网络信息; 响应于从所述第二电子设备接收到所述第二设备标识符和所述第二电子设备的网络信息,确定所述第一设备标识符是否与所述第二设备标识符相关联; 并且根据第一设备标识符与第二设备标识符相关联的确定,向第二电子设备发送第一电子设备的网络信息和/或向第一电子设备发送第二电子设备的网络信息 设备。

    LAYER TRANSFER TECHNOLOGY FOR SILICON CARBIDE
    5.
    发明申请
    LAYER TRANSFER TECHNOLOGY FOR SILICON CARBIDE 审中-公开
    硅碳膜转移技术

    公开(公告)号:WO2015084858A1

    公开(公告)日:2015-06-11

    申请号:PCT/US2014/068179

    申请日:2014-12-02

    Abstract: Devices that include a layer of silicon carbide and methods for making such devices are disclosed. A method includes obtaining a first silicon carbide wafer implanted with protons; applying a first layer of spin-on-glass over the first silicon carbide wafer; obtaining a first semiconductor substrate; bonding (i) the first layer of spin-on-glass to (ii) the first semiconductor substrate; and heating the first silicon carbide wafer to initiate splitting of the first silicon carbide wafer so that a first layer of silicon carbide remains over the first semiconductor substrate. A semiconductor device includes a semiconductor substrate; a first layer of spin-on-glass positioned over the semiconductor substrate; a first layer of silicon carbide positioned over the first layer of spin-on-glass; a second layer of spin-on-glass positioned over the first layer of silicon carbide; and a second layer of silicon carbide positioned over the second layer of spin-on-glass.

    Abstract translation: 公开了包括碳化硅层的装置和用于制造这种装置的方法。 一种方法包括获得植入质子的第一碳化硅晶片; 在第一碳化硅晶片上施加第一层旋涂玻璃; 获得第一半导体衬底; 将(i)第一层旋涂玻璃接合到(ii)第一半导体衬底; 以及加热所述第一碳化硅晶片以引发所述第一碳化硅晶片的分裂,使得第一碳化硅层保留在所述第一半导体衬底之上。 半导体器件包括半导体衬底; 位于半导体衬底上的第一层旋涂玻璃; 位于第一层旋涂玻璃上的第一层碳化硅; 位于第一层碳化硅上的第二层旋涂玻璃; 以及位于第二层旋涂玻璃上的第二层碳化硅。

    GATE-CONTROLLED CHARGE MODULATED DEVICE FOR CMOS IMAGE SENSORS
    6.
    发明申请
    GATE-CONTROLLED CHARGE MODULATED DEVICE FOR CMOS IMAGE SENSORS 审中-公开
    用于CMOS图像传感器的门控控制电荷调制装置

    公开(公告)号:WO2014205353A2

    公开(公告)日:2014-12-24

    申请号:PCT/US2014/043421

    申请日:2014-06-20

    Applicant: STRATIO, INC.

    Abstract: A device for sensing light includes a first semiconductor region doped with a dopant of a first type and a second semiconductor region doped with a dopant of a second type. The second semiconductor region is positioned above the first semiconductor region. The device includes a gate insulation layer; a gate, a source, and a drain. The second semiconductor region has a top surface that is positioned toward the gate insulation layer and a bottom surface that is positioned opposite to the top surface of the second semiconductor region. The second semiconductor region has an upper portion that includes the top surface of the second semiconductor region and a lower portion that includes the bottom surface of the second semiconductor region and is mutually exclusive with the upper portion. The first semiconductor region is in contact with both the upper portion and the lower portion of the second semiconductor region.

    Abstract translation: 用于感测光的装置包括掺杂有第一类型的掺杂剂的第一半导体区域和掺杂有第二类型的掺杂剂的第二半导体区域。 第二半导体区域位于第一半导体区域的上方。 该器件包括栅绝缘层; 一个门,一个源头和一个排水沟。 第二半导体区域具有朝向栅极绝缘层定位的顶表面和与第二半导体区域的顶表面相对定位的底表面。 第二半导体区域具有包括第二半导体区域的顶表面的上部和包括第二半导体区域的底表面并与上部相互排斥的下部。 第一半导体区域与第二半导体区域的上部和下部部分接触。

    GATE-CONTROLLED CHARGE MODULATED DEVICE FOR CMOS IMAGE SENSORS

    公开(公告)号:EP3011594B1

    公开(公告)日:2018-12-26

    申请号:EP14814462.9

    申请日:2014-06-20

    Applicant: Stratio, Inc.

    Abstract: A device for sensing light includes a first semiconductor region doped with a dopant of a first type and a second semiconductor region doped with a dopant of a second type. The second semiconductor region is positioned above the first semiconductor region. The device includes a gate insulation layer; a gate, a source, and a drain. The second semiconductor region has a top surface that is positioned toward the gate insulation layer and a bottom surface that is positioned opposite to the top surface of the second semiconductor region. The second semiconductor region has an upper portion that includes the top surface of the second semiconductor region and a lower portion that includes the bottom surface of the second semiconductor region and is mutually exclusive with the upper portion. The first semiconductor region is in contact with both the upper portion and the lower portion of the second semiconductor region.

    GATE-CONTROLLED CHARGE MODULATED DEVICE FOR CMOS IMAGE SENSORS
    9.
    发明公开
    GATE-CONTROLLED CHARGE MODULATED DEVICE FOR CMOS IMAGE SENSORS 有权
    GATEGESTEUERTE LADUNGSMODULIERTE VORRICHTUNGFÜRCMOS-BILDSENSOREN

    公开(公告)号:EP3011594A2

    公开(公告)日:2016-04-27

    申请号:EP14814462.9

    申请日:2014-06-20

    Applicant: Stratio, Inc.

    Abstract: A device for sensing light includes a first semiconductor region doped with a dopant of a first type and a second semiconductor region doped with a dopant of a second type. The second semiconductor region is positioned above the first semiconductor region. The device includes a gate insulation layer; a gate, a source, and a drain. The second semiconductor region has a top surface that is positioned toward the gate insulation layer and a bottom surface that is positioned opposite to the top surface of the second semiconductor region. The second semiconductor region has an upper portion that includes the top surface of the second semiconductor region and a lower portion that includes the bottom surface of the second semiconductor region and is mutually exclusive with the upper portion. The first semiconductor region is in contact with both the upper portion and the lower portion of the second semiconductor region.

    Abstract translation: 用于感测光的装置包括掺杂有第一类型的掺杂剂的第一半导体区域和掺杂有第二类型的掺杂剂的第二半导体区域。 第二半导体区域位于第一半导体区域的上方。 该器件包括栅极绝缘层; 一个门,一个源头和一个排水沟。 第二半导体区域具有朝向栅极绝缘层定位的顶表面和与第二半导体区域的顶表面相对定位的底表面。 第二半导体区域具有包括第二半导体区域的顶表面的上部和包括第二半导体区域的底表面并且与上部相互排斥的下部。 第一半导体区域与第二半导体区域的上部和下部两者接触。

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