公开(公告)号：WO03052824A2

公开(公告)日：2003-06-26

申请号：PCT/DE0204599

申请日：2002-12-16

Applicant: INFINEON TECHNOLOGIES AG ,  BARGSTAEDT-FRANKE SILKE ,  ESMARK KAI ,  GOSSNER HARALD ,  RIESS PHILIPP ,  STADLER WOLFGANG ,  STREIBL MARTIN ,  WENDEL MARTIN

Inventor： BARGSTAEDT-FRANKE SILKE ,  ESMARK KAI ,  GOSSNER HARALD ,  RIESS PHILIPP ,  STADLER WOLFGANG ,  STREIBL MARTIN ,  WENDEL MARTIN

IPC: H01L23/544 ,  H01L23/60 ,  H01L27/00

CPC classification number: H01L22/34 ,  H01L23/60 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: The invention relates to a method for determining the ESD/latch-up resistance of an integrated circuit, said method comprising the following steps: an integrated circuit (1, 2) and a test structure (N3) are simultaneously produced by means of the same process steps; electrical parameters of the test structure (N3) are measured; characteristic values are derived from the measured parameter values, said characteristic values characterising an ESD or latch-up characteristic curve associated with the integrated circuit (1, 2); and it is checked whether the characteristic values are respectively contained in a pre-determined range associated with the same. The ranges are selected in such a way that a desired ESD/latch-up resistance is achieved when the characteristic values are respectively contained in their range.

Abstract translation: 一种用于确定集成电路的ESD /闭锁强度等，其包括以下步骤的方法：共享通过相同的工艺步骤制造集成电路（1,2）和一个测试结构（N3），在该测试结构（N3）的电气参数的测量， 从所测量的参数值，其中所述集成电路中的一个的特征值（1，2）与ESD相关联或表征闩锁的特性曲线导出特征值，并且检查所述参数是否内的分配给它们的预定范围内的每个，所述区域 被选择为使得如果特性各自在它们的范围内，则存在期望的ESD /闭锁强度。

公开(公告)号：DE10356759A1

公开(公告)日：2004-12-16

申请号：DE10356759

申请日：2003-12-04

Applicant: BARGSTAEDT FRANKE SILKE ,  STADLER WOLFGANG ,  ESMARK KAI ,  STREIBL MARTIN ,  GIESSER HORST

Inventor： BARGSTAEDT FRANKE SILKE ,  STADLER WOLFGANG ,  ESMARK KAI ,  STREIBL MARTIN ,  GIESSER HORST

IPC: G01R31/30 ,  H01L23/544 ,  G01R31/3183 ,  H01L21/66 ,  H01L23/62

Abstract: A drain to source transient disturbance detector has a four layer CMOS (Complementary Metal Oxide Silicon) test structure with n+ and p+ diffusion in a p-well and p+ and n= diffusion in an n-well both in a p-substrate connected between a pulse generator creating disturbances and a current sensor detector. Includes INDEPENDENT CLAIMs for bipolar and biCMOS (bipolar Complementary Metal Oxide Silicon) technology versions and for capacitive or diode connection of the pulse generator.

公开(公告)号：DE19814125C1

公开(公告)日：1999-10-28

申请号：DE19814125

申请日：1998-03-30

Applicant: STREIBL MARTIN

Inventor： STREIBL MARTIN

IPC: H01L31/108 ,  H01L31/00 ,  G01J1/42 ,  H01L31/09

Abstract: The detector has a substrate (1) between a semiconductor system (2) and a detector structure (8), which operates as a frequency filter, so that a low-frequency photoluminescence signal (7) converted in the semiconductor system reaches the detector structure instead of a primary optic signal (6). An arrangement (5) for producing electric fields is provided in the semiconductor system, where the frequency change is controlled by an external voltage. The detector includes at least one arrangement for coupling in optical signals, a system for absorbing the optical signals, which emits light with a larger wavelength after the absorption, and a detector structure (8) for receiving the light with the larger wavelength. The absorption system is a semiconductor system (2), in which at least a part of the optical signals is converted to elementary excitations of the semiconductor, which can recombine within the semiconductor system through photoluminescence (7). A substrate (1) is arranged between the semiconductor system and the detector structure, which operates as a frequency filter, in such way, that not the primary optical signal (6), but the low-frequency photoluminescence signal converted in the semiconductor system, reaches the detector structure. An arrangement (5) for producing electric fields is provided in the semiconductor system, whereby the frequency change is controllable through an external voltage.

公开(公告)号：WO02059970A3

公开(公告)日：2003-08-07

申请号：PCT/DE0200177

申请日：2002-01-21

Applicant: INFINEON TECHNOLOGIES AG ,  DOLLINGER ANDREAS ,  KOBLMILLER HERBERT ,  MARK MICHAEL ,  STREIBL MARTIN ,  SCHULTHEISS VOLKER ,  WENDEL MARTIN ,  HOFER GUENTER ,  KRASSER GUENTER ,  PRAINSACK JOSEF ,  SCHUCHTER WALTER ,  STADLER WOLFGANG

Inventor： DOLLINGER ANDREAS ,  KOBLMILLER HERBERT ,  MARK MICHAEL ,  STREIBL MARTIN ,  SCHULTHEISS VOLKER ,  WENDEL MARTIN ,  HOFER GUENTER ,  KRASSER GUENTER ,  PRAINSACK JOSEF ,  SCHUCHTER WALTER ,  STADLER WOLFGANG

IPC: H01L23/62 ,  H01L27/02 ,  H01L29/78

CPC classification number: H01L27/0288

Abstract: The invention relates to a CMOS transistor (T) comprising a plurality of individual transistors (T1 Tn) which are connected in a parallel manner. Said individual transistors (T1- Tn) are respectively supplied with an additional series resistor (R). The above-mentioned circuit offers a protection against electrostatic re-charging combined with good high frequency properties of a CMOS transistor and is particularly suitable for analog circuits.

Abstract translation: 则表示（T）是CMOS晶体管，其包括具有多个并联连接的单独的晶体管（T1至Tn）。 各个晶体管（T1至Tn）设置有提供附加的串联电阻（R）。 连接防止静电放电与CMOS晶体管的良好的高频特性的保护所描述的电路，并且是用于模拟电路特别有用。

公开(公告)号：DE19944452A1

公开(公告)日：2001-04-12

申请号：DE19944452

申请日：1999-09-16

Applicant: BEIL FLORIAN ,  STREIBL MARTIN ,  WIXFORTH ACHIM

Inventor： BEIL FLORIAN ,  STREIBL MARTIN ,  WIXFORTH ACHIM

IPC: G01L1/00 ,  G01B17/00 ,  G01H9/00 ,  G01H11/00 ,  G01J3/28 ,  G01R33/02 ,  G06F3/033 ,  H03H9/145 ,  H03H9/64 ,  G01H17/00 ,  G01N21/41 ,  G06K11/14