公开(公告)号：DE102011086473A1

公开(公告)日：2012-05-24

申请号：DE102011086473

申请日：2011-11-16

Applicant: SAMSUNG ELECTRONICS CO LTD

Inventor： YUNHYEOK IM ,  CHUNGSUN LEE ,  TAEJE CHO

IPC: H01L23/049 ,  H01L21/50 ,  H01L23/24 ,  H01L23/64 ,  H01L25/16

Abstract: Die Erfindung bezieht sich auf eine Halbleiterpackung mit gestapelten Halbleiterchips, auf ein Halbleitermodul mit einer derartigen Packung, auf ein Verfahren zur Herstellung der Halbleiterpackung sowie auf ein elektronisches Bauelement, das ein derartiges Modul beinhaltet. Eine Halbleiterpackung gemäß der Erfindung beinhaltet ein Packungssubstrat (200) mit einem Durchkontakt (220s), wenigstens einen Halbleiterchip (100, 120), der auf dem Packungssubstrat gestapelt ist, einen thermischen Grenzflächenfilm (132), der auf dem Halbleiterchip gestapelt ist, eine Packungsabdeckung (300), die in Kontakt mit dem thermischen Grenzflächenfilm und über dem Halbleiterchip positioniert ist, und eine Packungshaftstruktur (310) zwischen dem Durchkontakt und einem Teil der Packungsabdeckung. Verwendung in der Halbleiterbauelementtechnologie.

公开(公告)号：US20150214089A1

公开(公告)日：2015-07-30

申请号：US14682231

申请日：2015-04-09

Applicant: SAMSUNG ELECTRONICS CO., LTD

Inventor： CHUNGSUN LEE ,  Jung-Seok AHN ,  Kwang-chul CHOI ,  Un-Byoung KANG ,  Jung-Hwan KIM ,  JOONSIK SOHN ,  JEON IL LEE

IPC: H01L21/683 ,  B32B37/18 ,  B32B37/12 ,  B32B38/10 ,  H01L21/02 ,  B32B38/04 ,  B32B37/24 ,  H01L21/304 ,  H01L21/768 ,  H01L23/00 ,  B32B37/26 ,  B32B38/16

CPC classification number: H01L21/6835 ,  B32B37/1284 ,  B32B37/18 ,  B32B37/24 ,  B32B37/26 ,  B32B38/04 ,  B32B38/10 ,  B32B38/162 ,  B32B2037/268 ,  B32B2315/08 ,  B32B2457/14 ,  H01L21/02057 ,  H01L21/02126 ,  H01L21/304 ,  H01L21/6836 ,  H01L21/76898 ,  H01L24/03 ,  H01L24/14 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68363 ,  H01L2221/68372 ,  H01L2221/68381 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/13023 ,  H01L2924/12042 ,  H01L2924/181 ,  Y10S438/977 ,  H01L2924/00

Abstract: A method for processing substrates includes providing a bonding layer between a substrate and a carrier to bond the substrate to the carrier, processing the substrate while the substrate is supported by the carrier, and removing the bonding layer to separate the substrate from the carrier. The bonding layer may include a thermosetting release layer and thermosetting glue layers, wherein at least one of the thermosetting glue layers is provided on each side of the thermosetting release layer.

Abstract translation: 一种处理衬底的方法包括：在衬底和载体之间提供接合层，以将衬底粘合到载体上，在衬底由载体支撑的同时处理衬底，以及去除结合层以使衬底与载体分离。 粘合层可以包括热固性剥离层和热固性胶层，其中至少一个热固性胶层设置在热固性剥离层的每一侧上。

公开(公告)号：US20230132272A1

公开(公告)日：2023-04-27

申请号：US17870898

申请日：2022-07-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： JUN YOUNG OH ,  UN-BYOUNG KANG ,  BYEONGCHAN KIM ,  JUMYONG PARK ,  CHUNGSUN LEE

IPC: H01L23/00 ,  H01L25/065

Abstract: The semiconductor device may include a substrate, a first insulating layer on a bottom surface of the substrate, an interconnection structure in the first insulating layer, a second insulating layer on a bottom surface of the first insulating layer, and a plurality of lower pads provided in the second insulating layer. Each lower pad may be provided such a width of a top surface thereof is smaller than a width of a bottom surface thereof. The lower pads may include first, second, and third lower pads. In a plan view, the first and third lower pads may be adjacent to center and edge portions of the substrate, respectively, and the second lower pad may be disposed therebetween. A width of a bottom surface of the second lower pad may be smaller than that of the first lower pad and may be larger than that of the third lower pad.

公开(公告)号：US20140210075A1

公开(公告)日：2014-07-31

申请号：US14147718

申请日：2014-01-06

Applicant: Samsung Electronics Co., Ltd

Inventor： CHUNGSUN LEE ,  Jung-Seok AHN ,  Kwang-chul CHOI ,  Un-Byoung KANG ,  Jung-Hwan KIM ,  JOONSIK SOHN ,  JEON IL LEE

IPC: H01L21/304 ,  H01L21/683

CPC classification number: H01L21/6835 ,  B32B37/1284 ,  B32B37/18 ,  B32B37/24 ,  B32B37/26 ,  B32B38/04 ,  B32B38/10 ,  B32B38/162 ,  B32B2037/268 ,  B32B2315/08 ,  B32B2457/14 ,  H01L21/02057 ,  H01L21/02126 ,  H01L21/304 ,  H01L21/6836 ,  H01L21/76898 ,  H01L24/03 ,  H01L24/14 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68363 ,  H01L2221/68372 ,  H01L2221/68381 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/13023 ,  H01L2924/12042 ,  H01L2924/181 ,  Y10S438/977 ,  H01L2924/00

Abstract: A method for processing substrates includes providing a bonding layer between a substrate and a carrier to bond the substrate to the carrier, processing the substrate while the substrate is supported by the carrier, and removing the bonding layer to separate the substrate from the carrier. The bonding layer may include a thermosetting release layer and thermosetting glue layers, wherein at least one of the thermosetting glue layers is provided on each side of the thermosetting release layer.

Abstract translation: 一种处理衬底的方法包括：在衬底和载体之间提供接合层，以将衬底粘合到载体上，在衬底由载体支撑的同时处理衬底，以及去除结合层以使衬底与载体分离。 粘合层可以包括热固性剥离层和热固性胶层，其中至少一个热固性胶层设置在热固性剥离层的每一侧上。

公开(公告)号：US20240222331A1

公开(公告)日：2024-07-04

申请号：US18473126

申请日：2023-09-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JIN-WOO PARK ,  UN-BYOUNG KANG ,  CHUNGSUN LEE

IPC: H01L25/065 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L24/03 ,  H01L24/05 ,  H01L24/09 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05687 ,  H01L2224/0569 ,  H01L2224/0903 ,  H01L2224/09152 ,  H01L2224/16014 ,  H01L2224/16148 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/81203 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/1431 ,  H01L2924/3511

Abstract: A semiconductor package includes a buffer chip configured to include a first dummy region and a second dummy region and to include first pads on rear surfaces of substrates of the first and second dummy regions; and a first core chip stacked at an upper portion of the buffer to include a bump 116 coupled to the first pad and positioned on an entire surface of the substrate, wherein the first pad is positioned in a line shape having a length including at least two bumps.

公开(公告)号：US20230290718A1

公开(公告)日：2023-09-14

申请号：US18199824

申请日：2023-05-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： JI-SEOK HONG ,  DONGWOO KIM ,  HYUNAH KIM ,  UN-BYOUNG KANG ,  CHUNGSUN LEE

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/31

CPC classification number: H01L23/49838 ,  H01L23/49822 ,  H01L21/4857 ,  H01L23/3128 ,  H01L23/49816

Abstract: Disclosed are interconnection structures, semiconductor packages including the same, and methods of fabricating the same. The interconnection structure comprises a first dielectric layer, a wiring pattern formed in the first dielectric layer, a portion of the wiring pattern exposed with respect to a top surface of the first dielectric layer, a second dielectric layer on the first dielectric layer, the second dielectric layer including an opening that exposes the exposed portion of the wiring pattern, a pad formed in the opening of the second dielectric layer, the pad including a base part that covers the exposed portion of the wiring pattern at a bottom of the opening and a sidewall part that extends upwardly along an inner lateral surface of the opening from the base part, a first seed layer interposed between the second dielectric layer and a first lateral surface of the sidewall part, the first seed layer being in contact with the first lateral surface and the second dielectric layer, and a second seed layer that conformally covers a second lateral surface of the sidewall part and a top surface of the base part, the second lateral surface being opposite to the first lateral surface the second dielectric layer.

公开(公告)号：US20220068785A1

公开(公告)日：2022-03-03

申请号：US17324569

申请日：2021-05-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： JI-SEOK HONG ,  DONGWOO KIM ,  HYUNAH KIM ,  UN-BYOUNG KANG ,  CHUNGSUN LEE

IPC: H01L23/498 ,  H01L23/31 ,  H01L21/48

Abstract: Disclosed are interconnection structures, semiconductor packages including the same, and methods of fabricating the same. The interconnection structure comprises a first dielectric layer, a wiring pattern formed in the first dielectric layer, a portion of the wiring pattern exposed with respect to a top surface of the first dielectric layer, a second dielectric layer on the first dielectric layer, the second dielectric layer including an opening that exposes the exposed portion of the wiring pattern, a pad formed in the opening of the second dielectric layer, the pad including a base part that covers the exposed portion of the wiring pattern at a bottom of the opening and a sidewall part that extends upwardly along an inner lateral surface of the opening from the base part, a first seed layer interposed between the second dielectric layer and a first lateral surface of the sidewall part, the first seed layer being in contact with the first lateral surface and the second dielectric layer, and a second seed layer that conformally covers a second lateral surface of the sidewall part and a top surface of the base part, the second lateral surface being opposite to the first lateral surface the second dielectric layer.

公开(公告)号：US20210028217A1

公开(公告)日：2021-01-28

申请号：US16802683

申请日：2020-02-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： YONGHOE CHO ,  CHUNGSUN LEE ,  YOONHA JUNG ,  CHAJEA JO

IPC: H01L27/146 ,  H01L23/00 ,  H01L23/48 ,  H01L21/683

Abstract: Disclosed are a semiconductor package and a method of fabricating the same. The semiconductor package may include a semiconductor chip structure, a transparent substrate disposed on the semiconductor chip structure, a dam placed on an edge of the semiconductor chip structure and between the semiconductor chip structure and the transparent substrate, and an adhesive layer interposed between the dam and the semiconductor chip structure. The semiconductor chip structure may include an image sensor chip and a logic chip, which are in contact with each other, and the image sensor chip may be closer to the transparent substrate than the logic chip.

公开(公告)号：US20240170449A1

公开(公告)日：2024-05-23

申请号：US18213018

申请日：2023-06-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HYOUNGJOO LEE ,  SANG-SICK PARK ,  CHUNGSUN LEE ,  SEUNGYOON JUNG

IPC: H01L23/00 ,  H01L25/065

CPC classification number: H01L24/83 ,  H01L24/08 ,  H01L24/09 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/0801 ,  H01L2224/0903 ,  H01L2224/09517 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/81097 ,  H01L2224/81203 ,  H01L2224/83097 ,  H01L2224/83203 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2924/351

Abstract: A method includes providing a first structure, forming a connection pad on the first structure, forming a preliminary connection member on the connection pad, forming an adhesion layer on the first structure, the adhesion layer covering the preliminary connection member, removing a portion of the adhesion layer to expose an exposure surface of the preliminary connection member, providing a second structure, forming a chip pad and a dummy pad on the second structure, and covering the chip pad and the dummy pad with the adhesion layer that has been formed on the first structure. A thickness of the dummy pad is greater than a thickness of the chip pad.

公开(公告)号：US20240120251A1

公开(公告)日：2024-04-11

申请号：US18213851

申请日：2023-06-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： JIN-WOO PARK ,  UN-BYOUNG KANG ,  CHUNGSUN LEE

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L23/3157 ,  H01L21/56 ,  H01L24/08 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/16145 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/81203 ,  H01L2224/92125 ,  H10B80/00

Abstract: Disclosed are semiconductor packages and their fabrication methods. The semiconductor package comprises a base semiconductor chip, a chip structure on the base semiconductor chip, a connection terminal between the base semiconductor chip and the chip structure, and a molding layer surrounding the chip structure and the connection terminal. The chip structure includes a first semiconductor chip including a first frontside pad and a first backside pad, and a second semiconductor including a second frontside pad and a second backside pad. A lateral surface of the first semiconductor chip is aligned with that of the second semiconductor chip. The first backside pad and the second frontside pad partially overlap each other when viewed in plan while being in direct contact with each other. The first backside pad and the second frontside pad include the same metal and are formed into a single unitary piece.