公开(公告)号：KR20200129854A

公开(公告)日：2020-11-18

申请号：KR20190054877

申请日：2019-05-10

Applicant: SAMSUNG ELECTRONICS CO LTD

Inventor： HOJONG KIM ,  DONGWOO KIM

IPC: G06F1/32 ,  G06F1/26

Abstract: 다양한실시예들에따른전자장치는제1 배터리, 제2 배터리, 전력관리회로, 상기제1 배터리의완충상태에서의제1 완충전압값 및상기제2 배터리의완충상태에서의제2 완충전압값에대한정보를저장하도록구성된메모리및 상기제1 배터리또는상기제2 배터리에게전력을제공하는외부전자장치와의연결을검출하고, 상기검출에응답하여, 상기제1 완충전압값이상기제2 완충전압값보다높은것으로식별되면, 상기제1 배터리를상기전력관리회로와전기적으로연결하고상기제2 배터리를상기전력관리회로와전기적으로단절하고, 상기전력관리회로와전기적으로연결된상기제1 배터리를상기외부전자장치로부터획득되는전력에기반하여충전하도록구성된프로세서를포함할수 있다.

公开(公告)号：US20220359678A1

公开(公告)日：2022-11-10

申请号：US17552446

申请日：2021-12-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： GYEOM KIM ,  JINBUM KIM ,  DONGWOO KIM ,  DONGSUK SHIN ,  SANGMOON LEE ,  SEUNG HUN LEE

IPC: H01L29/417 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  H01L21/02 ,  H01L29/40 ,  H01L29/66

Abstract: A semiconductor device includes a substrate including an active pattern, a channel pattern and a source/drain pattern on the active pattern, a gate electrode provided on the channel pattern and extended in a first direction, and an active contact coupled to the source/drain pattern. The active contact includes a buried portion buried in the source/drain pattern and a contact portion on the buried portion. The buried portion includes an expansion portion provided in a lower portion of the source/drain pattern and a vertical extension portion connecting the contact portion to the expansion portion.

公开(公告)号：US20160315193A1

公开(公告)日：2016-10-27

申请号：US15138914

申请日：2016-04-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： DONGWOO KIM ,  SEUNGHUN LEE ,  SUNJUNG KIM ,  HYUNJUNG LEE ,  BONYOUNG KOO

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/165 ,  H01L29/08 ,  H01L29/161

CPC classification number: H01L29/7848 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/7853

Abstract: A semiconductor device can include a substrate and a fin body that protrudes from a surface of the substrate. The fin body can include a lower portion having a first lattice structure and an upper portion, separated from the lower portion by a boundary, the upper portion having a second lattice structure that is different than the first lattice structure. An epitaxially grown epitxial layer can be on the lower and upper portions.

Abstract translation: 半导体器件可以包括从衬底的表面突出的衬底和鳍体。 翅片本体可以包括具有第一格子结构的下部和与下部分开边界的上部，上部具有不同于第一格子结构的第二格子结构。 外延生长的外延层可以在下部和上部。

公开(公告)号：US20230290718A1

公开(公告)日：2023-09-14

申请号：US18199824

申请日：2023-05-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： JI-SEOK HONG ,  DONGWOO KIM ,  HYUNAH KIM ,  UN-BYOUNG KANG ,  CHUNGSUN LEE

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/31

CPC classification number: H01L23/49838 ,  H01L23/49822 ,  H01L21/4857 ,  H01L23/3128 ,  H01L23/49816

Abstract: Disclosed are interconnection structures, semiconductor packages including the same, and methods of fabricating the same. The interconnection structure comprises a first dielectric layer, a wiring pattern formed in the first dielectric layer, a portion of the wiring pattern exposed with respect to a top surface of the first dielectric layer, a second dielectric layer on the first dielectric layer, the second dielectric layer including an opening that exposes the exposed portion of the wiring pattern, a pad formed in the opening of the second dielectric layer, the pad including a base part that covers the exposed portion of the wiring pattern at a bottom of the opening and a sidewall part that extends upwardly along an inner lateral surface of the opening from the base part, a first seed layer interposed between the second dielectric layer and a first lateral surface of the sidewall part, the first seed layer being in contact with the first lateral surface and the second dielectric layer, and a second seed layer that conformally covers a second lateral surface of the sidewall part and a top surface of the base part, the second lateral surface being opposite to the first lateral surface the second dielectric layer.

公开(公告)号：US20220352309A1

公开(公告)日：2022-11-03

申请号：US17714695

申请日：2022-04-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JINBUM KIM ,  DAHYE KIM ,  DONGMYOUNG KIM ,  DONGWOO KIM ,  YONGJUN NAM ,  SANGMOON LEE ,  INGYU JANG ,  SUJIN JUNG

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/10

Abstract: A semiconductor device includes a substrate having an active region extending in a first direction; a gate structure disposed on the substrate, intersecting the active region, and extending in a second direction; channel layers disposed on the active region to be spaced apart from each other in a third direction, perpendicular to an upper surface of the substrate, and to be surrounded by the gate structure; source/drain regions disposed on both sides of the gate structure and connected to the channel layers; air gap regions located between the source/drain regions and the active region and spaced apart from each other in the third direction; and semiconductor layers alternately disposed with the air gap regions in the third direction and defining the air gap regions, wherein lower ends of the source/drain regions are located on a level lower than an uppermost air gap region.

公开(公告)号：US20220068785A1

公开(公告)日：2022-03-03

申请号：US17324569

申请日：2021-05-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： JI-SEOK HONG ,  DONGWOO KIM ,  HYUNAH KIM ,  UN-BYOUNG KANG ,  CHUNGSUN LEE

IPC: H01L23/498 ,  H01L23/31 ,  H01L21/48

Abstract: Disclosed are interconnection structures, semiconductor packages including the same, and methods of fabricating the same. The interconnection structure comprises a first dielectric layer, a wiring pattern formed in the first dielectric layer, a portion of the wiring pattern exposed with respect to a top surface of the first dielectric layer, a second dielectric layer on the first dielectric layer, the second dielectric layer including an opening that exposes the exposed portion of the wiring pattern, a pad formed in the opening of the second dielectric layer, the pad including a base part that covers the exposed portion of the wiring pattern at a bottom of the opening and a sidewall part that extends upwardly along an inner lateral surface of the opening from the base part, a first seed layer interposed between the second dielectric layer and a first lateral surface of the sidewall part, the first seed layer being in contact with the first lateral surface and the second dielectric layer, and a second seed layer that conformally covers a second lateral surface of the sidewall part and a top surface of the base part, the second lateral surface being opposite to the first lateral surface the second dielectric layer.

公开(公告)号：US20240234551A1

公开(公告)日：2024-07-11

申请号：US18539355

申请日：2023-12-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jangwoo PARK ,  DONGWOO KIM ,  JINBUM KIM

IPC: H01L29/732 ,  H01L23/522

CPC classification number: H01L29/732 ,  H01L23/522 ,  H01L29/0673

Abstract: A semiconductor device includes first, second, and third epitaxial layers sequentially stacked on a substrate and a first diffusion prevention layer provided in at least one of regions between the first and second epitaxial layers and between the second and third epitaxial layers. The first and third epitaxial layers have a first conductivity type, and the second epitaxial layer has a second conductivity type. The first diffusion prevention layer is configured to prevent an impurity in the second epitaxial layer from being diffused. The first, second, and third epitaxial layers include first, second, and third active patterns, respectively, which are respective provided in upper portions thereof and on collector, base, and emitter regions, respectively, of the substrate.