中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

12 records (took 0.027 seconds)

    SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
    2.
    发明专利
    SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 未知

    公开(公告)号：SG10201804930VA

    公开(公告)日：2019-04-29

    申请号：SG10201804930V

    申请日：2018-06-08

    Applicant: SAMSUNG ELECTRONICS CO LTD

    Inventor： DONG CHAN SUH ,  SANGMOON LEE ,  YIHWAN KIM ,  WOO BIN SONG ,  DONGSUK SHIN ,  SEUNG RYUL LEE

    IPC: H01L29/772 ,  H01L21/335

    Abstract: A method for manufacturing a semiconductor device and a semiconductor device, the method including forming an active pattern on a substrate such that the active pattern includes sacrificial patterns and semiconductor patterns alternately and repeatedly stacked on the substrate; and forming first spacer patterns at both sides of each of the sacrificial patterns by performing an oxidation process, wherein the first spacer patterns correspond to oxidized portions of each of the sacrificial patterns, wherein the sacrificial patterns include a first semiconductor material containing impurities, wherein the semiconductor patterns include a second semiconductor material different from the first semiconductor material, and wherein the impurities include an element different from semiconductor elements of the first semiconductor material and the second semiconductor material. FIG. 7

    SEMICONDUCTOR DEVICES INCLUDING SOURCE/DRAIN REGIONS HAVING MULTIPLE EPITAXIAL PATTERNS
    5.
    发明申请
    SEMICONDUCTOR DEVICES INCLUDING SOURCE/DRAIN REGIONS HAVING MULTIPLE EPITAXIAL PATTERNS 有权
    半导体器件，包括具有多个外延模式的源/漏区

    公开(公告)号：US20150380553A1

    公开(公告)日：2015-12-31

    申请号：US14673519

    申请日：2015-03-30

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： KEUM SEOK PARK ,  JUNGHO YOO ,  JINYEONG JOE ,  BONYOUNG KOO ,  DONGSUK SHIN ,  HONGSIK YOON ,  BYEONGCHAN LEE

    IPC: H01L29/78 ,  H01L29/165

    CPC classification number: H01L29/7848 ,  H01L21/02532 ,  H01L21/02636 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/785

    Abstract: A semiconductor device includes an active pattern protruding from a substrate, a gate structure crossing over the active pattern, and source/drain regions disposed on the active pattern at opposite sides of the gate structure. Each of the source/drain regions includes a first epitaxial pattern contacting the active pattern and a second epitaxial pattern on the, first epitaxial pattern. The first epitaxial pattern comprises a material having a lattice constant which is the same as that of the substrate, and the second epitaxial pattern comprises a material having a lattice constant greater than that of the first epitaxial pattern.

    Abstract translation: 半导体器件包括从衬底突出的有源图案，在有源图案上交叉的栅极结构以及设置在栅极结构的相对侧上的有源图案上的源极/漏极区域。 源极/漏极区域中的每一个包括接触有源图案的第一外延图案和第一外延图案上的第二外延图案。 第一外延图案包括具有与衬底相同的晶格常数的材料，并且第二外延图案包括具有大于第一外延图案的晶格常数的晶格常数的材料。

    SEMICONDUCTOR DEVICE
    6.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20250056861A1

    公开(公告)日：2025-02-13

    申请号：US18583006

    申请日：2024-02-21

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： SOOJIN JEONG ,  MYUNG GIL KANG ,  DONGWON KIM ,  BEOMJIN PARK ,  DONGSUK SHIN ,  HYUN-KWAN YU ,  WOOSUK CHOI ,  SEUNGPYO HONG

    IPC: H01L29/66 ,  H01L21/8238 ,  H01L23/528 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

    Abstract: A semiconductor device includes a substrate including an active pattern, a channel pattern on the active pattern, the channel pattern including a plurality of semiconductor patterns that are spaced apart from each other, a source/drain pattern electrically connected to the plurality of semiconductor patterns, an inner gate electrode between adjacent first and second semiconductor patterns of the plurality of semiconductor patterns, an inner gate insulating layer between the inner gate electrode and the first and second semiconductor patterns, an inner high-k dielectric layer between the inner gate electrode and the inner gate insulating layer, and an inner spacer between the inner gate insulating layer and the source/drain pattern. As the inner gate insulating layer includes an inner gate spacer, the inner gate electrode may stably fill the inner gate space. As a result, the electrical characteristics of the semiconductor device may be improved.

    SEMICONDUCTOR MEMORY DEVICE
    8.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20210057419A1

    公开(公告)日：2021-02-25

    申请号：US16833919

    申请日：2020-03-30

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： DONGSUK SHIN ,  JIYOUNG KIM ,  HOKYUN AN ,  CHAN MIN LEE ,  EUNJU CHO ,  HUI-JUNG KIM ,  JOONGCHAN SHIN ,  TAEHYUN AN ,  HYUNGEUN CHOI ,  YOOSANG HWANG ,  KISEOK LEE

    IPC: H01L27/108

    Abstract: A semiconductor memory device includes a substrate having a cell region and a contact region with a peripheral circuit region, first and second stacks on the cell region, and a first peripheral transistor on the peripheral circuit region. Each of the first and second stacks includes semiconductor patterns stacked, in a vertical direction, on the cell region, bit lines stacked in the vertical direction on the cell region and respectively connected to first ends of the semiconductor patterns, each of the bit lines extending, in a horizontal direction with respect to the upper surface of the substrate, from the cell region to the contact region, and a word line disposed adjacent to the semiconductor patterns and extending in the vertical direction from the cell region of the substrate. The first peripheral transistor is disposed between the bit lines of the first stack and the bit lines of the second stack.

Patent Agency Ranking