公开(公告)号：SG10202007886XA

公开(公告)日：2021-05-28

申请号：SG10202007886X

申请日：2020-08-18

Applicant: SAMSUNG ELECTRONICS CO LTD

Inventor： JOONGCHAN SHIN ,  CHANGKYU KIM ,  HUI-JUNG KIM ,  ILJAE SHIN ,  TAEHYUN AN ,  KISEOK LEE ,  EUNJU CHO ,  HYUNGEUN CHOI ,  SUNG-MIN PARK ,  AHRAM LEE ,  SANGYEON HAN ,  YOOSANG HWANG

Abstract: A three-dimensional semiconductor memory device includes first semiconductor patterns, which are vertically spaced apart from each other on a substrate, each of which includes first and second end portions spaced apart from each other, and first and second side surfaces spaced apart from each other to connect the first and second end portions, first and second source/drain regions disposed in each of the first semiconductor patterns and adjacent to the first and second end portions, respectively, a channel region in each of the first semiconductor patterns and between the first and second source/drain regions, a first word line adjacent to the first side surfaces and the channel regions and vertically extended, and a gate insulating layer interposed between the first word line and the first side surfaces. The gate insulating layer may be extended to be interposed between the first source/drain regions.

公开(公告)号：US20210057419A1

公开(公告)日：2021-02-25

申请号：US16833919

申请日：2020-03-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： DONGSUK SHIN ,  JIYOUNG KIM ,  HOKYUN AN ,  CHAN MIN LEE ,  EUNJU CHO ,  HUI-JUNG KIM ,  JOONGCHAN SHIN ,  TAEHYUN AN ,  HYUNGEUN CHOI ,  YOOSANG HWANG ,  KISEOK LEE

IPC: H01L27/108

Abstract: A semiconductor memory device includes a substrate having a cell region and a contact region with a peripheral circuit region, first and second stacks on the cell region, and a first peripheral transistor on the peripheral circuit region. Each of the first and second stacks includes semiconductor patterns stacked, in a vertical direction, on the cell region, bit lines stacked in the vertical direction on the cell region and respectively connected to first ends of the semiconductor patterns, each of the bit lines extending, in a horizontal direction with respect to the upper surface of the substrate, from the cell region to the contact region, and a word line disposed adjacent to the semiconductor patterns and extending in the vertical direction from the cell region of the substrate. The first peripheral transistor is disposed between the bit lines of the first stack and the bit lines of the second stack.