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    Semiconductor Memory Devices
    1.
    发明专利
    Semiconductor Memory Devices 未知

    公开(公告)号：SG10201900899UA

    公开(公告)日：2019-09-27

    申请号：SG10201900899U

    申请日：2019-01-31

    Applicant: SAMSUNG ELECTRONICS CO LTD

    Inventor： KISEOK LEE ,  BONG-SOO KIM ,  JIYOUNG KIM ,  HUI-JUNG KIM ,  SEOKHAN PARK ,  HUNKOOK LEE ,  YOOSANG HWANG

    IPC: H01L27/108 ,  H01L23/528

    Abstract: Semiconductor memory devices may include first and second stacks on a substrate and first and second interconnection lines on the first and second stacks. Each of the first and second stacks may include semiconductor patterns vertically stacked on the substrate, conductive lines connected to the semiconductor patterns, respectively, and a gate electrode that is adjacent to the semiconductor patterns and extends in a vertical direction. The first stack may include a first conductive line and a first gate electrode, and the second stack may include a second conductive line and a second gate electrode. Lower surfaces of the first and second conductive lines may be coplanar. The first interconnection line may be electrically connected to at least one of the first and second conductive lines. The second interconnection line may be electrically connected to at least one of the first and second gate electrodes. FIG. 5

    INTEGRATED CIRCUIT DEVICES
    2.
    发明专利
    INTEGRATED CIRCUIT DEVICES 未知

    公开(公告)号：SG10201803879XA

    公开(公告)日：2019-04-29

    申请号：SG10201803879X

    申请日：2018-05-08

    Applicant: SAMSUNG ELECTRONICS CO LTD

    Inventor： JUN-HYEOK AHN ,  EUN-JUNG KIM ,  HUI-JUNG KIM ,  KI-SEOK LEE ,  BONG-SOO KIM ,  MYEONG-DONG LEE ,  SUNG-HEE HAN ,  YOO-SANG HWANG

    IPC: H01L21/768 ,  H01L23/528

    Abstract: OF THE DISCLOSURE An integrated circuit device may include a pair of line structures. Each line structure may a of lines over substrate a horizontal direction a of capping respectively the of conductive lines. The integrated circuit device may include a conductive plug between the pair of line structures and a metal silicide film contacting a top surface of the conductive plug between the pair of insulating capping patterns. The conductive plug may have a first width between pair conductive and second between pair insulating capping in second direction to first direction, where the second width is greater than the first width. FIG. 2A

    Three-Dimensional Semiconductor Memory Device
    3.
    发明专利
    Three-Dimensional Semiconductor Memory Device 未知

    公开(公告)号：SG10202007886XA

    公开(公告)日：2021-05-28

    申请号：SG10202007886X

    申请日：2020-08-18

    Applicant: SAMSUNG ELECTRONICS CO LTD

    Inventor： JOONGCHAN SHIN ,  CHANGKYU KIM ,  HUI-JUNG KIM ,  ILJAE SHIN ,  TAEHYUN AN ,  KISEOK LEE ,  EUNJU CHO ,  HYUNGEUN CHOI ,  SUNG-MIN PARK ,  AHRAM LEE ,  SANGYEON HAN ,  YOOSANG HWANG

    Abstract: A three-dimensional semiconductor memory device includes first semiconductor patterns, which are vertically spaced apart from each other on a substrate, each of which includes first and second end portions spaced apart from each other, and first and second side surfaces spaced apart from each other to connect the first and second end portions, first and second source/drain regions disposed in each of the first semiconductor patterns and adjacent to the first and second end portions, respectively, a channel region in each of the first semiconductor patterns and between the first and second source/drain regions, a first word line adjacent to the first side surfaces and the channel regions and vertically extended, and a gate insulating layer interposed between the first word line and the first side surfaces. The gate insulating layer may be extended to be interposed between the first source/drain regions.

    Semiconductor Memory Devices
    5.
    发明专利
    Semiconductor Memory Devices 未知

    公开(公告)号：SG10201804042RA

    公开(公告)日：2019-03-28

    申请号：SG10201804042R

    申请日：2018-05-14

    Applicant: SAMSUNG ELECTRONICS CO LTD

    Inventor： HUI-JUNG KIM ,  MIN HEE CHO ,  BONG-SOO KIM ,  JUNSOO KIM ,  SATORU YAMADA ,  WONSOK LEE ,  YOOSANG HWANG

    IPC: H01L29/41 ,  H01L21/8242 ,  H01L27/108

    Abstract: Semiconductor memory devices are provided. A semiconductor memory device includes an isolation layer in a first trench and a first gate electrode portion on the isolation layer. The semiconductor memory device includes a second gate electrode portion in a second trench. In some embodiments, the second gate electrode portion is wider, in a direction, than the first gate electrode portion. Moreover, in some embodiments, an upper region of the second trench is spaced apart from the first trench by a greater distance, in the direction, than a lower region of the second trench. Related methods of forming semiconductor memory devices are also provided. FIG. 1

    SEMICONDUCTOR MEMORY DEVICE
    6.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20240349492A1

    公开(公告)日：2024-10-17

    申请号：US18543279

    申请日：2023-12-18

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： MYEONG-DONG LEE ,  SEUNG-BO KO ,  KEUNNAM KIM ,  JONGMIN KIM ,  HUI-JUNG KIM ,  TAEJIN PARK ,  DONGHYUK AHN ,  KISEOK LEE ,  MINYOUNG LEE ,  INHO CHA

    IPC: H10B12/00

    CPC classification number: H10B12/485 ,  H10B12/02 ,  H10B12/315 ,  H10B12/34

    Abstract: A semiconductor memory device include first and second active patterns extending in a first direction and spaced apart from each other in a second direction crossing the first direction. The first and second active patterns include a first and second edge portions spaced apart from each other in the first direction, and a center portion therebetween. Bit line node contacts are on the center portions. Bit lines are on the bit line node contacts and extend in a third direction crossing the first and second directions. The center portions of the first and second active patterns are sequentially disposed in the second direction. Each of the bit line node contacts has a first width at a level of a top surface, a second width at a level of a bottom surface, and a third width between the top and bottom surfaces less than the first and second widths.

    SEMICONDUCTOR MEMORY DEVICE
    7.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20210057419A1

    公开(公告)日：2021-02-25

    申请号：US16833919

    申请日：2020-03-30

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： DONGSUK SHIN ,  JIYOUNG KIM ,  HOKYUN AN ,  CHAN MIN LEE ,  EUNJU CHO ,  HUI-JUNG KIM ,  JOONGCHAN SHIN ,  TAEHYUN AN ,  HYUNGEUN CHOI ,  YOOSANG HWANG ,  KISEOK LEE

    IPC: H01L27/108

    Abstract: A semiconductor memory device includes a substrate having a cell region and a contact region with a peripheral circuit region, first and second stacks on the cell region, and a first peripheral transistor on the peripheral circuit region. Each of the first and second stacks includes semiconductor patterns stacked, in a vertical direction, on the cell region, bit lines stacked in the vertical direction on the cell region and respectively connected to first ends of the semiconductor patterns, each of the bit lines extending, in a horizontal direction with respect to the upper surface of the substrate, from the cell region to the contact region, and a word line disposed adjacent to the semiconductor patterns and extending in the vertical direction from the cell region of the substrate. The first peripheral transistor is disposed between the bit lines of the first stack and the bit lines of the second stack.

    SEMICONDUCTOR MEMORY DEVICE AND A METHOD OF FABRICATING THE SAME
    8.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND A METHOD OF FABRICATING THE SAME 有权

    公开(公告)号：US20220375941A1

    公开(公告)日：2022-11-24

    申请号：US17574666

    申请日：2022-01-13

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： KISEOK LEE ,  HUI-JUNG KIM ,  MIN HEE CHO

    IPC: H01L27/108 ,  H01L29/786

    Abstract: A semiconductor memory device including: a stack structure including a plurality of layers that are vertically stacked on a substrate, each of the plurality of layers including a word line, a channel layer, and a data storage element electrically connected to the channel layer; and a bit line that vertically extends on one side of the stack structure, wherein the word line includes: a first conductive line that extends in a first direction; and a gate electrode that protrudes in a second direction from the first conductive line, the second direction intersecting the first direction, wherein the channel layer is on the gate electrode, and wherein the bit line includes a connection part electrically connected to the channel layer.

    VARIABLE RESISTANCE MEMORY DEVICE
    10.
    发明申请
    VARIABLE RESISTANCE MEMORY DEVICE 有权

    公开(公告)号：US20210159277A1

    公开(公告)日：2021-05-27

    申请号：US17167851

    申请日：2021-02-04

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： HUI-JUNG KIM ,  KISEOK LEE ,  KEUNNAM KIM ,  YOOSANG HWANG

    IPC: H01L27/24 ,  H01L45/00

    Abstract: Disclosed is a variable resistance memory device including a first conductive line extending in a first direction parallel to a top surface of the substrate, memory cells spaced apart from each other in the first direction on a side of the first conductive line and connected to the first conductive line, and second conductive lines respectively connected to the memory cells. Each second conductive line is spaced apart in a second direction from the first conductive line. The second direction is parallel to the top surface of the substrate and intersects the first direction. The second conductive lines extend in a third direction perpendicular to the top surface of the substrate and are spaced apart from each other in the first direction. Each memory cell includes a variable resistance element and a select element that are positioned at a same level horizontally arranged in the second direction.

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