公开(公告)号：US20240276713A1

公开(公告)日：2024-08-15

申请号：US18537987

申请日：2023-12-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeonil Lee ,  Kyunghwan Lee ,  Juho Lee

IPC: H10B12/00 ,  H01L29/423 ,  H01L29/788

CPC classification number: H10B12/485 ,  H01L29/42324 ,  H01L29/7889 ,  H10B12/315 ,  H10B12/482 ,  H10B12/488

Abstract: A semiconductor memory device includes a memory cell that extends in a first horizontal direction, a second horizontal direction that intersects the first horizontal direction, and a vertical direction. The memory cell includes a first transistor including a first channel structure, a second transistor including a second channel structure, a charge storage element electrically connected to a first end of the second channel structure and adjacent to the first channel structure a first bit line electrically connected to a first end of the first channel structure and that extends in the second horizontal direction, a selection line electrically connected to a second end of the first channel structure and that extends in the second horizontal direction, a second bit line electrically connected to a second end of the second channel structure and that extends in the second horizontal direction, and a gate line that extends in the vertical direction.

公开(公告)号：US20250149508A1

公开(公告)日：2025-05-08

申请号：US18674207

申请日：2024-05-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeonil Lee ,  Seryeun Yang ,  Dongkyun Lim

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L23/538 ,  H10B12/00 ,  H10B80/00

Abstract: A semiconductor device includes a first chip structure that includes a memory structure and a cell routing interconnection structure that is electrically connected to the memory structure, a second chip structure that is on the first chip structure and includes a first peripheral circuit, a second peripheral circuit, a first peripheral routing interconnection structure that is electrically connected to the first peripheral circuit and the cell routing interconnection structure, and a second peripheral routing interconnection structure that is electrically connected to the second peripheral circuit, and a connection structure that extends into the first chip structure and the second chip structure, where the connection structure includes: a first connection pad, a second connection pad that overlaps the first connection pad, and an intermediate connection structure that is between the first connection pad and the second connection pad and is electrically connected to the second peripheral routing interconnection structure.

公开(公告)号：US12199015B2

公开(公告)日：2025-01-14

申请号：US17574902

申请日：2022-01-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeonjin Lee ,  Jongmin Lee ,  Jeonil Lee

IPC: H01L21/00 ,  H01L21/768 ,  H01L23/48 ,  H01L25/065 ,  H10B99/00 ,  H01L23/00

Abstract: A semiconductor device according to some example embodiments includes a substrate, an insulating structure covering the substrate, a transistor between the substrate and the insulating structure, a via insulating layer extending through the insulating structure and the substrate, a plurality of via structures extending through the via insulating layer, a plurality of conductive structures respectively connected to the plurality of via structures, and a plurality of bumps respectively connected to the conductive structures.

公开(公告)号：US11844207B2

公开(公告)日：2023-12-12

申请号：US17579919

申请日：2022-01-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeonil Lee ,  Youngjun Kim ,  Jinbum Kim

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/0335 ,  H10B12/37 ,  H10B12/482

Abstract: A semiconductor device including an active pattern; a gate structure connected to the active pattern; a bit line structure connected to the active pattern; a buried contact connected to the active pattern; a contact pattern covering the buried contact; a landing pad connected to the contact pattern; and a capacitor structure connected to the landing pad, wherein the buried contact includes a first growth portion and a second growth portion spaced apart from each other, and the landing pad includes an interposition portion between the first growth portion and the second growth portion.

公开(公告)号：US12217958B2

公开(公告)日：2025-02-04

申请号：US16807702

申请日：2020-03-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keunwook Shin ,  Janghee Lee ,  Seunggeol Nam ,  Hyeonjin Shin ,  Hyunseok Lim ,  Alum Jung ,  Kyung-Eun Byun ,  Jeonil Lee ,  Yeonchoo Cho

IPC: C23C16/02 ,  C23C16/26 ,  H01L21/02

Abstract: A method of pre-treating a substrate on which graphene will be directly formed may include pre-treating the substrate using a pre-treatment gas including at least a carbon source and hydrogen.

公开(公告)号：US12183660B2

公开(公告)日：2024-12-31

申请号：US17736212

申请日：2022-05-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeonil Lee ,  Jongmin Lee ,  Jimin Choi ,  Yeonjin Lee

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/532 ,  H01L23/535

Abstract: A semiconductor device includes a substrate including a first surface, and a second surface opposing the first surface. A via insulating layer extending through the substrate is disposed. A through-silicon via extending through the via insulating layer is disposed. The center of the through-silicon via is misaligned from the center of the via insulating layer. A blocking layer is disposed on the first surface. A first insulating layer is disposed on the blocking layer. A contact plug contacting the through-silicon via and extending through the first insulating layer and the blocking layer is disposed.

公开(公告)号：US20240324237A1

公开(公告)日：2024-09-26

申请号：US18608149

申请日：2024-03-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeonil Lee ,  Kyunghwan Lee

IPC: H10B53/20 ,  H01L21/28 ,  H01L29/51 ,  H01L29/78 ,  H10B51/10 ,  H10B51/20 ,  H10B51/40 ,  H10B53/10 ,  H10B53/40

CPC classification number: H10B53/20 ,  H01L29/40111 ,  H01L29/516 ,  H01L29/78391 ,  H10B51/10 ,  H10B51/20 ,  H10B51/40 ,  H10B53/10 ,  H10B53/40

Abstract: A three-dimensional (3D) semiconductor memory device includes a plurality of memory cells stacked in a vertical direction, each of the plurality of memory cells including a cell transistor and a cell capacitor. The cell capacitor includes a first electrode connected to a first source/drain region of the cell transistor, wherein a through hole is formed in the first electrode and the inner surface of the first electrode is formed in a shape having concave portions and convex portions in plan view, a capacitor insulating layer in the through hole, and a second electrode in the capacitor insulating layer and filling the through hole.

公开(公告)号：US20240324234A1

公开(公告)日：2024-09-26

申请号：US18430291

申请日：2024-02-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeonil Lee ,  Kyunghwan Lee ,  Youngin Goh ,  Yukio Hayakawa

IPC: H10B51/20 ,  H10B51/30

CPC classification number: H10B51/20 ,  H10B51/30

Abstract: A 3D FeRAM is provided. The 3D FeRAM includes a semiconductor patterns stacked in a vertical direction on a substrate and spaced apart from each other in a first horizontal direction, bit lines on first side surface of the semiconductor patterns, extending in the first horizontal direction, and spaced apart from each other in the vertical direction, first electrodes on second side surfaces of the semiconductor patterns and spaced apart from each other in both the vertical direction and the first horizontal direction, a ferroelectric layer on the first electrodes, second electrodes on the ferroelectric layers, extending in the first horizontal direction, and spaced apart from each other in the vertical direction, and word lines between two adjacent semiconductor patterns extending in the vertical direction.

公开(公告)号：US20250157948A1

公开(公告)日：2025-05-15

申请号：US19023084

申请日：2025-01-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minjung Choi ,  Yeonjin Lee ,  Jeonil Lee ,  Jongmin Lee

IPC: H01L23/00 ,  H01L21/78 ,  H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L23/58

Abstract: A semiconductor device includes; a semiconductor substrate including a chip area and a scribe lane area, a low-k layer on the semiconductor substrate, an interlayer insulating layer on the low-k layer, a trench area in the scribe lane area, a gap-fill insulating layer in the trench area and vertically extending from the semiconductor substrate through the low-k layer and the interlayer insulating layer to expose an upper surface of the gap-fill insulating layer through the interlayer insulating layer, and a first metal liner covering a side surface of the gap-fill insulating layer and disposed between the gap-fill insulating layer and the low-k layer and between the gap-fill insulating layer and the interlayer insulating layer.

公开(公告)号：US12230587B2

公开(公告)日：2025-02-18

申请号：US17706013

申请日：2022-03-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minjung Choi ,  Yeonjin Lee ,  Jeonil Lee ,  Jongmin Lee

IPC: H01L21/78 ,  H01L23/00 ,  H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L23/58

Abstract: A semiconductor device includes; a semiconductor substrate including a chip area and a scribe lane area, a low-k layer on the semiconductor substrate, an interlayer insulating layer on the low-k layer, a trench area in the scribe lane area, a gap-fill insulating layer in the trench area and vertically extending from the semiconductor substrate through the low-k layer and the interlayer insulating layer to expose an upper surface of the gap-fill insulating layer through the interlayer insulating layer, and a first metal liner covering a side surface of the gap-fill insulating layer and disposed between the gap-fill insulating layer and the low-k layer and between the gap-fill insulating layer and the interlayer insulating layer.