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公开(公告)号:EP4177933A1
公开(公告)日:2023-05-10
申请号:EP22189897.6
申请日:2022-08-11
Applicant: Samsung Electronics Co., Ltd.
Inventor: KIM, Hyuncheol , KIM, Yongseok , WOO, Dongsoo , LEE, Kyunghwan , LEE, Minjun
IPC: H01L21/28 , G11C11/22 , H01L29/51 , H01L29/66 , H01L29/739 , H01L29/78 , H10B51/20 , H10B80/00 , H01L29/423
Abstract: A semiconductor memory device may include a substrate (10), first (20) and second (30) impurity regions on the substrate, first (40) and second (50) gate insulating layers sequentially stacked on the substrate and extended in a direction between the first and second impurity regions, and a gate electrode (60) on the second gate insulating layer. The first and second impurity regions may have different conductivity types from each other, a bottom surface of the first gate insulating layer may be in direct contact with a top surface of the substrate, and the second gate insulating layer may include a ferroelectric material.
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公开(公告)号:EP4307345A1
公开(公告)日:2024-01-17
申请号:EP23185512.3
申请日:2023-07-14
Applicant: Samsung Electronics Co., Ltd.
Inventor: LIM, Suhwan , KIM, Yongseok , KIM, Juhyung , LEE, Minjun
Abstract: The present disclosure provides methods, apparatuses, and systems for operating and manufacturing a semiconductor device. In some embodiments, a semiconductor device (1) includes a stack structure (ST) including interlayer insulating layers (33) and gate electrodes (75), a channel layer (52) disposed inside a hole (39) penetrating through the stack structure, a data storage layer (48) disposed between the stack structure and the channel layer, data storage patterns (45) disposed between the data storage layer and the gate electrodes, and dielectric layers (42) disposed between the data storage patterns and the gate electrodes. The interlayer insulating layers and the gate electrodes are alternately and repeatedly stacked in a first direction. A first material of the data storage layer is different from a second material of the data storage patterns.
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