中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

20 records (took 0.031 seconds)

    THREE-DIMENSIONAL SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
    3.
    发明公开
    THREE-DIMENSIONAL SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 审中-公开

    公开(公告)号：EP4254478A1

    公开(公告)日：2023-10-04

    申请号：EP22211519.8

    申请日：2022-12-05

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： LEE, Kyunghwan ,  PARK, Sungil ,  PARK, Jae Hyun ,  HA, Daewon

    IPC: H01L21/822 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/092 ,  H01L29/417 ,  H01L29/66 ,  H01L29/775 ,  H01L27/088 ,  H01L21/8234

    Abstract: A three-dimensional semiconductor device comprises a first active region (AR1) on a substrate (100) and including a lower channel pattern (CH1) and a lower source/drain pattern (SD1) connected to the lower channel pattern, a second active region (AR2) stacked on the first active region and including an upper channel pattern (CH2) and an upper source/drain pattern (SD2) connected to the upper channel pattern, a gate electrode structure (GE) on the lower channel pattern and the upper channel pattern, a first active contact (AC1) electrically connected to the lower source/drain pattern, an upper separation structure (USS) between the first active contact and the upper source/drain pattern, a second active contact (AC2) electrically connected to the upper source/drain pattern, and a lower separation structure (LSS) between the second active contact and the lower source/drain pattern.

    THREE-DIMENSIONAL NON-VOLATILE MEMORY DEVICE INCLUDING HORIZONTAL CHANNEL REGION
    4.
    发明公开
    THREE-DIMENSIONAL NON-VOLATILE MEMORY DEVICE INCLUDING HORIZONTAL CHANNEL REGION 审中-公开

    公开(公告)号：EP4243588A1

    公开(公告)日：2023-09-13

    申请号：EP23160697.1

    申请日：2023-03-08

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： HA, Daewon ,  LEE, Kyunghwan ,  PARK, Hyunmog

    IPC: H10B51/20 ,  H10B51/10

    Abstract: A three-dimensional non-volatile memory device (100) includes a memory cell array (MCA) including a plurality of memory cells (MC) repeatedly arranged in a first lateral direction (X), a second lateral direction (Y), and a vertical direction (Z) on a substrate (110). The first lateral direction and the second lateral direction are parallel to a main surface of the substrate and perpendicular to each other, and the vertical direction is perpendicular to the main surface of the substrate. The memory cell array includes a plurality of horizontal channel regions (130) and a vertical word line (WL). The plurality of horizontal channel regions extend in the first lateral direction on the substrate. The plurality of horizontal channel regions overlap each other and are apart from each other in the vertical direction. The vertical word line passes through the plurality of horizontal channel regions in the vertical direction.

    ELECTRONIC DEVICE COMPRISING PLURALITY OF BATTERIES AND OPERATING METHOD THEREFOR
    7.
    发明公开
    ELECTRONIC DEVICE COMPRISING PLURALITY OF BATTERIES AND OPERATING METHOD THEREFOR 审中-实审

    公开(公告)号：EP4395115A1

    公开(公告)日：2024-07-03

    申请号：EP23798074.3

    申请日：2023-11-06

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： KANG, Sangwoo ,  LEE, Kyunghwan

    IPC: H02J7/00 ,  H01M10/44 ,  H02M3/00

    Abstract: An electronic device according to an embodiment may include a first battery, a second battery, a first charging circuit configured to provide power of a first voltage to the first battery, a second charging circuit configured to provide power of a second voltage to the second battery, a first limiter disposed between the first battery and the second charging circuit, and a processor. The processor according to an embodiment may be configured to identify the first voltage to be applied to the first battery. The processor according to an embodiment may be configured to request power of an input voltage corresponding to twice the first voltage from an external power source based on the first voltage, The processor according to an embodiment may be configured to, based on applying the input voltage corresponding to twice the first voltage provided from the external power source to the first charging circuit, control the first charging circuit to supply the power of the first voltage to the first battery. The processor according to an embodiment may be configured to, based on applying the input voltage corresponding to twice the first voltage provided from the external power source to the second charging circuit, control the second charging circuit to supply the power of the second voltage to the second battery.

    ELECTRONIC DEVICE COMPRISING PLURALITY OF BATTERIES, AND OPERATING METHOD THEREOF
    8.
    发明公开
    ELECTRONIC DEVICE COMPRISING PLURALITY OF BATTERIES, AND OPERATING METHOD THEREOF 审中-实审

    公开(公告)号：EP4372959A1

    公开(公告)日：2024-05-22

    申请号：EP23772399.4

    申请日：2023-09-26

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： LEE, Kyunghwan

    IPC: H02J7/00 ,  H01M50/284

    Abstract: An electronic device (201, 301, 302) according to an embodiment may include a first battery (281), a second battery (282), a charging circuit (380, 381) configured to supply power to the first battery through a first path and supply power to the second battery through a second path, and a processor (220). According to an embodiment, the processor may be configured to control the charging circuit to generate a current corresponding to a sum of a first threshold current of the first battery and a second threshold current of the second battery based on power received from a power transmitter (305). According to an embodiment, the processor may be configured to, based on the current, control the charging circuit to supply a first current to the first battery through a first path and a second current to the second battery through a second path. According to an embodiment, the processor may be configured to identify the second current supplied to the second battery through the second path. According to an embodiment, the processor may be configured to, based on identifying that the second current exceeds the second threshold current, control the charging circuit so as to reduce the magnitude of the second current supplied to the second battery. In addition, various embodiments are possible.

    OPERATION METHOD OF USER EQUIPMENT USING CONNECTED MODE DISCONTINUOUS RECEPTION
    9.
    发明公开
    OPERATION METHOD OF USER EQUIPMENT USING CONNECTED MODE DISCONTINUOUS RECEPTION 审中-公开

    公开(公告)号：EP4181584A1

    公开(公告)日：2023-05-17

    申请号：EP22207407.2

    申请日：2022-11-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： KANG, Inheon ,  LEE, Kyunghwan

    IPC: H04W52/02 ,  H04W24/10

    Abstract: The devices, systems, methods, and techniques described herein provide for efficient operation of a user equipment (UE) configured to support mobility mechanisms while using connected mode discontinuous reception (CDRX). In some aspects, a UE configured to use CDRX may measure objects according to a No DRX minimum measurement period (e.g., a minimum measurement period configured when no DRX is used). Because the No DRX minimum measurement period may be shorter than a DRX minimum measurement period, the UE may be able to measure objects more frequently and improve mobility performance. Further, although the UE may perform measurements according to the No DRX minimum measurement period, the UE may still report the measurements according to a DRX minimum measurement period. Thus, the UE may report measurements less frequently, and the UE may sleep during more off-durations of a CDRX cycle, resulting in reduced power consumption.

    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE
    10.
    发明公开
    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：EP3483935A1

    公开(公告)日：2019-05-15

    申请号：EP18190010.1

    申请日：2018-08-21

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： LEE, Kyunghwan ,  KIM, Yongseok ,  KIM, Byoung-Taek ,  KIM, Tae Hun ,  SEO, Dongkyun ,  LIM, Junhee

    IPC: H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582

    Abstract: A three-dimensional semiconductor memory device includes an electrode structure including gate electrodes and insulating layers, which are alternately stacked on a substrate, a semiconductor pattern extending in a first direction substantially perpendicular to a top surface of the substrate and penetrating the electrode structure, a tunnel insulating layer disposed between the semiconductor pattern and the electrode structure, a blocking insulating layer disposed between the tunnel insulating layer and the electrode structure, and a charge storing layer disposed between the blocking insulating layer and the tunnel insulating layer. The charge storing layer includes a plurality of first charge trap layers having a first energy band gap, and a second charge trap layer having a second energy band gap larger than the first energy band gap. The first charge trap layers are embedded in the second charge trap layer between the gate electrodes and the semiconductor pattern.

Patent Agency Ranking