公开(公告)号：US11984529B2

公开(公告)日：2024-05-14

申请号：US16930819

申请日：2020-07-16

Applicant: Sensor Electronic Technology, Inc.

Inventor： Mohamed Lachab

IPC: H01L33/06 ,  H01L29/00 ,  H01L33/10 ,  H01L33/02 ,  H01L33/14 ,  H01L33/32

CPC classification number: H01L33/06 ,  H01L29/00 ,  H01L33/10 ,  H01L33/025 ,  H01L33/145 ,  H01L33/32

Abstract: A heterostructure for an optoelectronic device is disclosed. The heterostructure includes an active region including at least one quantum well and at least one barrier and an electron blocking layer located adjacent to the active region, wherein the electron blocking layer includes a region of graded composition. An asymmetric p-type superlattice layer is located adjacent to the electron blocking layer, wherein the p-type superlattice includes at least one superlattice period comprising a set of wells and a set of barriers. A thickness of at least one of: each well in the set of wells or each barrier in the set of barriers varies along a length of the p-type superlattice.

公开(公告)号：US20230299238A1

公开(公告)日：2023-09-21

申请号：US18122513

申请日：2023-03-16

Applicant: Sensor Electronic Technology, Inc.

Inventor： Rakesh B. Jain ,  Mohamed Lachab ,  Joseph Dion ,  Brandon Alexander Robinson ,  Devendra Diwan ,  Mark Geppert

IPC: H01L33/32 ,  H01L33/22 ,  H01L33/12

CPC classification number: H01L33/325 ,  H01L33/22 ,  H01L33/12

Abstract: A solution for fabricating a semiconductor structure and the corresponding semiconductor structure are provided. The semiconductor structure includes a plurality of semiconductor layers grown over a substrate using a set of epitaxial growth periods. During each epitaxial growth period, a first semiconductor layer having one of: a tensile stress or a compressive stress is grown followed by growth of a second semiconductor layer having the other of: the tensile stress or the compressive stress directly on the first semiconductor layer.

公开(公告)号：US20190103509A1

公开(公告)日：2019-04-04

申请号：US16148360

申请日：2018-10-01

Applicant: Sensor Electronic Technology, Inc.

Inventor： Mohamed Lachab

IPC: H01L33/06 ,  H01L33/14 ,  H01L33/32 ,  H01L33/02 ,  H01L33/10

Abstract: A heterostructure for an optoelectronic device is disclosed. The heterostructure includes an active region including at least one quantum well and at least one barrier and an electron blocking layer located adjacent to the active region, wherein the electron blocking layer includes a region of graded composition. An asymmetric p-type superlattice layer is located adjacent to the electron blocking layer, wherein the p-type superlattice includes at least one superlattice period comprising a set of wells and a set of barriers. A thickness of at least one of: each well in the set of wells or each barrier in the set of barriers varies along a length of the p-type superlattice.

公开(公告)号：US20200350465A1

公开(公告)日：2020-11-05

申请号：US16930819

申请日：2020-07-16

Applicant: Sensor Electronic Technology, Inc.

Inventor： Mohamed Lachab

IPC: H01L33/06 ,  H01L33/10 ,  H01L29/00

Abstract: A heterostructure for an optoelectronic device is disclosed. The heterostructure includes an active region including at least one quantum well and at least one barrier and an electron blocking layer located adjacent to the active region, wherein the electron blocking layer includes a region of graded composition. An asymmetric p-type superlattice layer is located adjacent to the electron blocking layer, wherein the p-type superlattice includes at least one superlattice period comprising a set of wells and a set of barriers. A thickness of at least one of: each well in the set of wells or each barrier in the set of barriers varies along a length of the p-type superlattice.