METHOD AND SYSTEM FOR PROCESSING EXCEPTION

    公开(公告)号:JPH03116236A

    公开(公告)日:1991-05-17

    申请号:JP13513890

    申请日:1990-05-24

    Abstract: PURPOSE: To simplify a system by activating an exception procedure developed for a signal instruction by a unique exception processing procedure. CONSTITUTION: An exception display test bit field generated by an ALU is connected with the input of a latched MUX 110, a control port is connected with the control field of a microcode in a level 5, and the output is connected with a second input port of an AND gate 106. The output of a first decoder DEC I flashes a pipe line and inhibits the writing operation of a level 5 when an exception condition is discovered. The MUX 110 transmits a specific exception display test bit to be tested about an instruction family during execution, and when the exception condition is generated, the AND gate 106 is opened, a microcode filed of (m) bits in a level 5 is decoded, and a control signal for executing a non-paring restarting procedure execution is generated. Thus, the system can be simplified.

    DATA PROCESSOR BRANCH PROCESSING METHOD

    公开(公告)号:JPH03116235A

    公开(公告)日:1991-05-17

    申请号:JP13242590

    申请日:1990-05-22

    Abstract: PURPOSE: To fetch an exact next instruction in a pipe line by comparing a branching prediction bit with a branching condition bit, and testing the error of the prediction. CONSTITUTION: Two cases related with a condition branching instruction are identified according to whether or not the previous instructions are included in a present family, and when a branching condition bit(BCB) is not matched to a branching prediction bit(BPB) from a hierachy PID register 120, branching is a predicted error, and the output of a comparator 124 opens an AND gate 128. Afterwards, an (n) bit hierachy 4 microcode field is transmitted to a decoder (DECA) 139, and a control signal necessary for executing a branching predicting mechanism is generated. Thus, the exact next instruction can be fetched.

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