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    DATA PROCESSOR BRANCH PROCESSING METHOD
    3.
    发明专利
    DATA PROCESSOR BRANCH PROCESSING METHOD 失效

    公开(公告)号：JPH03116235A

    公开(公告)日：1991-05-17

    申请号：JP13242590

    申请日：1990-05-22

    Applicant: TANDEM COMPUTERS INC

    Inventor： ROBAATO ERU JIYAADEIIN ,  SHIYANON JIEI RINCHI ,  FUIRITSUPU AARU MANERA ,  ROBAATO DABURIYUU HOOSUTO

    IPC: G06F9/38

    Abstract: PURPOSE: To fetch an exact next instruction in a pipe line by comparing a branching prediction bit with a branching condition bit, and testing the error of the prediction. CONSTITUTION: Two cases related with a condition branching instruction are identified according to whether or not the previous instructions are included in a present family, and when a branching condition bit(BCB) is not matched to a branching prediction bit(BPB) from a hierachy PID register 120, branching is a predicted error, and the output of a comparator 124 opens an AND gate 128. Afterwards, an (n) bit hierachy 4 microcode field is transmitted to a decoder (DECA) 139, and a control signal necessary for executing a branching predicting mechanism is generated. Thus, the exact next instruction can be fetched.

    CACHE MEMORY SUPPORTING NON-ALIGNMENT ACCESS
    5.
    发明专利
    CACHE MEMORY SUPPORTING NON-ALIGNMENT ACCESS 失效

    公开(公告)号：JPH02288931A

    公开(公告)日：1990-11-28

    申请号：JP27360289

    申请日：1989-10-20

    Applicant: TANDEM COMPUTERS INC

    Inventor： ROBAATO DABURIYUU HOOSUTO

    IPC: G06F12/08 ,  G06F12/0862 ,  G06F12/0886 ,  G06F12/0895 ,  G06F12/109

    Abstract: PURPOSE: To take out words of a prescribed sequence in one memory cycle by taking the word addressed by a received memory word address as a first read data value. CONSTITUTION: Words of a prescribed multi-word data unit(MWDU) 14 are stored in another memory unit, and this unit has each storage locations 12 addressed by a multi-word field(MWF) of word addresses of words in the prescribed MWDU 14. Hardware for address processing uses the word address of the first word of a prescribed sequence to generate one set or changed MWF provided in the address port of the memory unit. A data supply device connects the output of the memory unit to an output bus and transfers sequential words to this bus in the correct order. Thus, words of the prescribed sequence are taken out in one memory cycle.

    SYNCHRONOUS METHOD AND APPARATUS FOR A PLURALITY OF PROCESSORS
    7.
    发明专利
    SYNCHRONOUS METHOD AND APPARATUS FOR A PLURALITY OF PROCESSORS 失效

    公开(公告)号：JPH01258057A

    公开(公告)日：1989-10-16

    申请号：JP28230688

    申请日：1988-11-08

    Applicant: TANDEM COMPUTERS INC

    Inventor： ROBAATO DABURIYUU HOOSUTO

    IPC: G06F11/18 ,  G06F9/52 ,  G06F11/16 ,  G06F15/17 ,  G11C29/00

    Abstract: PURPOSE: To guarantee the maintainability of data by counting events such as writing operations instructed for every processor and interrupting a processing when the number of event to be counted of a pertinent processor is larger than the number of event to be counted of an other processor. CONSTITUTION: Synchronizing requests are received by CPU 6, 8 and 10 and each of the CPUs executes parts of different codes. The CPU 6 becomes a wating state because an event 4 is detected. The CPU 8 and the CPU 10 become waiting states by the detection of an event 5 and the detection of an event 6, respectively. Because the number of event to be counted of the CPU 6 is smaller than that of the CPU 10, the CPU 6 restarts the execution of an instruction and becomes the waiting state by the detection of an event 5. When the CPU 6 is still delayed than the CPU 10, an execution instruction is restarted, the event 5 is detected and the CPU 6 becomes the waiting state again. Also the CPU 8 takes the same processing sequence. Thus, when the count of each event becomes equal, each processor restarts an execution by the synchronizing external interruption signal at a point of common time.

    COMPUTER MEMORY SYSTEM
    10.
    发明专利
    COMPUTER MEMORY SYSTEM 失效

    公开(公告)号：JPH03135642A

    公开(公告)日：1991-06-10

    申请号：JP17609390

    申请日：1990-07-03

    Applicant: TANDEM COMPUTERS INC

    Inventor： ROBAATO DABURIYUU HOOSUTO ,  AAJIEI KEI SHIYAA ,  AI KOO YAMAMOTO

    IPC: G06F12/08 ,  G06F12/02 ,  G06F12/10

    Abstract: PURPOSE: To perform high-speed memory read and write by providing a comparator for judging whether or not a memory location indicated by an address request is included inside the plural memory locations. CONSTITUTION: In order to process a new address request 001110, row bits inside the address request 8 and the contents of virtual/physical (CAMtag) 7 are compared. In this case, the row bits inside the address request 8 are 001 and the contents of the CAMtag 7 are 101 on the other hand. Thus, since the comparator 11 indicates that a CAM error is present, it means that the newly arrived address request 8 is for a row different from the row asserted at present. Then, when the comparator 11 indicates an error, registers 6 and 7 are updated. Thus, cache fill time is reduced and a valid write band width is enlarged.

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