公开(公告)号：MX153417A

公开(公告)日：1986-10-07

申请号：MX19722883

申请日：1983-05-10

Applicant: TANDEM COMPUTERS INC

Inventor： MENZIES PHILIP ROBERT ,  ATWOOD JOHN G JR ,  HINDERS DAVID LEE ,  GREIG DAVID A

IPC: H04M3/00 ,  H04B7/15 ,  H04B7/185 ,  H04B1/59 ,  H04H5/00

Abstract: Satellite communications system for computer networks. A multi-node, satellite communications system employing a modified broadcast system is disclosed for use with distributed computer networks. The system involves a plurality of computer systems (network nodes) each capable of transmitting to any other node at a single unique frequency, but capable of receiving from all other nodes simultaneously. Each node in the n-node network comprises a single transmitter with up to n-1 receivers, with each node capable of arbitrating a plurality of requests for transmission access. The invention encompasses a method of communicating digital information in a network of geographically distributed computers.

公开(公告)号：CA1176338A

公开(公告)日：1984-10-16

申请号：CA391313

申请日：1981-12-01

Applicant: TANDEM COMPUTERS INC

Inventor： KATZMAN JAMES A ,  BARTLETT JOEL F ,  BIXLER RICHARD M ,  DAVIDOW WILLIAM H ,  DESPOTAKIS JOHN A ,  GRAZIANO PETER J ,  GREEN MICHAEL D ,  GREIG DAVID A ,  HAYASHI STEVEN J ,  MACKIE DAVID R ,  MCEVOY DENNIS L ,  TREYBIG JAMES G ,  WIERENGA STEVEN W

IPC: G06F3/00

Abstract: A multiprocessor system the kind in which two or more separate processor modules are interconnected for parallel processing includes two redundant interprocessor buses dedicated exclusively to interprocessor communication. Any processor module may send information to any other processor module by either bus. The buses are shared in use by the processor modules on a time-sharing basis. Use of each bus is controlled by a special bus controller. The multiprocessor system includes an input/output system having multi-port device controllers and input/output buses connecting each device controller for access by the input/output channels of at least two different processor modules. Each device controller includes logic which insures that only one port is selected for access at a time. The multiprocessor system includes a distributed power supply system which insures uninterrupted operation of the remainder of the multiprocessor system in the event of a failure of a power supply for a part of the system. The distributed power supply system includes a separate power supply for each processor module and two separate power supplies for each device controller. Either one of the two power supplies provides the entire power for the device controller in the event the other power supply fails. The distributed power supply system permits any processor module or device controller to be powered down so that on-line maintenance can be performed in a power-off condition while the rest of the multiprocessor system is on-line and functional. The multiprocessor system includes a memory system in which the memory of each processor module is divided into four logical address areas -- user data, system data, user code and system code. The memory system includes a map which translates logical addresses to physical addresses and which coacts with the multiprocessor system to bring pages from secondary memory into primary main memory as required to implement a virtual memory system. The map also provides a protection function. It provides inherent protection among users in a multiprogramming environment, isolates programs from data and protects system programs from the actions of user programs. The map also provides a reference history information for each logical page as an aid to efficient memory management by the operating system. The multiprocessor system includes in the memory of each processor module an error detection and correction system which detects all single bit and double bit errors and which corrects all single bit errors in semiconductor memory storage.

公开(公告)号：GB2121651B

公开(公告)日：1986-02-05

申请号：GB8312889

申请日：1983-05-11

Applicant: TANDEM COMPUTERS INC

Inventor： MENZIES PHILIP R ,  ATWOOD JOHN G ,  HINDERS DAVID L ,  GREIG DAVID A

IPC: H04M3/00 ,  H04B7/15 ,  H04B7/185 ,  H04B1/50

Abstract: Satellite communications system for computer networks. A multi-node, satellite communications system employing a modified broadcast system is disclosed for use with distributed computer networks. The system involves a plurality of computer systems (network nodes) each capable of transmitting to any other node at a single unique frequency, but capable of receiving from all other nodes simultaneously. Each node in the n-node network comprises a single transmitter with up to n-1 receivers, with each node capable of arbitrating a plurality of requests for transmission access. The invention encompasses a method of communicating digital information in a network of geographically distributed computers.

公开(公告)号：BR8302470A

公开(公告)日：1984-01-17

申请号：BR8302470

申请日：1983-05-11

Applicant: TANDEM COMPUTERS INC

Inventor： MENZIES PHILIP ROBERT ,  ATWOOD JOHN G ,  HINDERS DAVID LEE ,  GREIG DAVID A

IPC: H04M3/00 ,  H04B7/15 ,  H04B7/185 ,  H04B7/00

Abstract: Satellite communications system for computer networks. A multi-node, satellite communications system employing a modified broadcast system is disclosed for use with distributed computer networks. The system involves a plurality of computer systems (network nodes) each capable of transmitting to any other node at a single unique frequency, but capable of receiving from all other nodes simultaneously. Each node in the n-node network comprises a single transmitter with up to n-1 receivers, with each node capable of arbitrating a plurality of requests for transmission access. The invention encompasses a method of communicating digital information in a network of geographically distributed computers.

公开(公告)号：FI831621A0

公开(公告)日：1983-05-10

申请号：FI831621

申请日：1983-05-10

Applicant: TANDEM COMPUTERS INC

Inventor： MENZIES PHILIP ROBERT ,  ATWOOD JR JOHN G ,  HINDERS DAVID LEE ,  GREIG DAVID A

IPC: H04M3/00 ,  H04B7/15 ,  H04B7/185 ,  H04B

Abstract: Satellite communications system for computer networks. A multi-node, satellite communications system employing a modified broadcast system is disclosed for use with distributed computer networks. The system involves a plurality of computer systems (network nodes) each capable of transmitting to any other node at a single unique frequency, but capable of receiving from all other nodes simultaneously. Each node in the n-node network comprises a single transmitter with up to n-1 receivers, with each node capable of arbitrating a plurality of requests for transmission access. The invention encompasses a method of communicating digital information in a network of geographically distributed computers.

公开(公告)号：CA1142619A

公开(公告)日：1983-03-08

申请号：CA391318

申请日：1981-12-01

Applicant: TANDEM COMPUTERS INC

Inventor： KATZMAN JAMES A ,  BARTLETT JOEL F ,  BIXLER RICHARD M ,  DAVIDOW WILLIAM H ,  DESPOTAKIS JOHN A ,  GRAZIANO PETER J ,  GREEN MICHAEL D ,  GREIG DAVID A ,  HAYASHI STEVEN J ,  MACKIE DAVID R ,  MCEVOY DENNIS L ,  TREYBIG JAMES G ,  WIERENGA STEVEN W

IPC: G06F11/30

Abstract: A multiprocessor system the kind in which two or more separate processor modules are interconnected for parallel processing includes two redundant interprocessor buses dedicated exclusively to interprocessor communication. Any processor module may send information to any other processor module by either bus. The buses are shared in use by the processor modules on a time-sharing basis. Use of each bus is controlled by a special bus controller. The multiprocessor system includes an input/output system having multi-port device controllers and input/output buses connecting each device controller for access by the input/output channels of at least two different processor modules. Each device controller includes logic which insures that only one port is selected for access at a time. The multiprocessor system includes a distributed power supply system which insures uninterrupted operation of the remainder of the multiprocessor system in the event of a failure of a power supply for a part of the system. The distributed power supply system includes a separate power supply for each processor module and two separate power supplies for each device controller. Either one of the two power supplies provides the entire power for the device controller in the event the other power supply fails. The distributed power supply system permits any processor module or device controller to be powered down so that on-line maintenance can be performed in a power-off condition while the rest of the multiprocessor system is on-line and functional. The multiprocessor system includes a memory system in which the memory of each processor module is divided into four logical address areas -- user data, system data, user code and system code. The memory system includes a map which translates logical addresses to physical addresses and which coacts with the multiprocessor system to bring pages from secondary memory into primary main memory as required to implement a virtual memory system. The map also provides a protection function. It provides inherent protection among users in a multiprogramming environment, isolates programs from data and protects system programs from the actions of user programs. The map also provides a reference history information for each logical page as an aid to efficient memory management by the operating system. The multiprocessor system includes in the memory of each processor module an error detection and correction system which detects all single bit and double bit errors and which corrects all single bit errors in semiconductor memory storage.

公开(公告)号：CA1185670A

公开(公告)日：1985-04-16

申请号：CA455620

申请日：1984-05-31

Applicant: TANDEM COMPUTERS INC

Inventor： KATZMAN JAMES A ,  BARTLETT JOEL F ,  BIXLER RICHARD M ,  DAVIDOW WILLIAM H ,  DESPOTAKIS JOHN A ,  GRAZIANO PETER J ,  GREEN MICHAEL D ,  GREIG DAVID A ,  HAYASHI STEVEN J ,  MACKIE DAVID R ,  MCEVOY DENNIS L ,  TREYBIG JAMES G ,  WIERENGA STEVEN W

IPC: G06F3/00

Abstract: A multiprocessor system the kind in which two or more separate processor modules are interconnected for parallel processing includes two redundant interprocessor buses dedicated exclusively to interprocessor communication. Any processor module may send information to any other processor module by either bus. The buses are shared in use by the processor modules on a time-sharing basis. Use of each bus is controlled by a special bus controller. The multiprocessor system includes an input/output system having multi-port device controllers and input/output buses connecting each device controller for access by the input/output channels of at least two different processor modules. Each device controller includes logic which insures that only one port is selected for access at a time. The multiprocessor system includes a distributed power supply system which insures uninterrupted operation of the remainder of the multlprocessor system in the event of a failure of a power supply for a part of the system. The distributed power supply system includes a separate power supply for each processor module and two separate power supplies for each device controller. Either one of the two power supplies provides the entire power for the device controller in the event the other power supply fails. The distributed power supply system permits any processor module or device controller to be powered down so that on-line maintenance can be performed in a power-off condition while the rest of the multiprocessor system is on-line and functional. The multiprocessor system includes a memory system in which the memory of each processor module is divided into four logical address areas -- user data, system data, user code and system code. The memory system includes a map which translates logical addresses to physical addresses and which coacts with the multiprocessor system to bring pages from secondary memory into primary main memory as required to implement a virtual memory system. The map also provides a protection function. It provides inherent protection among users in a multiprogramming environment, isolates programs from data and protects system programs from the actions of user programs. The map also provides a reference history information for each logical page as an aid to efficient memory management by the operating system. The multiprocessor system includes in the memory of each processor module an error detection and correction system which detects all single bit and double bit errors and which corrects all single bit errors in semiconductor memory storage.

公开(公告)号：CA1147417A

公开(公告)日：1983-05-31

申请号：CA391320

申请日：1981-12-01

Applicant: TANDEM COMPUTERS INC

Inventor： KATZMAN JAMES A ,  BARTLETT JOEL F ,  BIXLER RICHARD M ,  DAVIDOW WILLIAM H ,  DESPOTAKIS JOHN A ,  GRAZIANO PETER J ,  GREEN MICHAEL D ,  GREIG DAVID A ,  HAYASHI STEVEN J ,  MACKIE DAVID R ,  MCEVOY DENNIS L ,  TREYBIG JAMES G ,  WIERENGA STEVEN W

IPC: G06F15/16

Abstract: A multiprocessor system the kind in which two or more separate processor modules are interconnected for parallel processing includes two redundant interprocessor buses dedicated exclusively to interprocessor communication. Any processor module may send information to any other processor module by either bus. The buses are shared in use by the processor modules on a time-sharing basis. Use of each bus is controlled by a special bus controller. The multiprocessor system includes an input/output system having multi-port device controllers and input/output buses connecting each device controller for access by the input/output channels of at least two different processor modules. Each device controller includes logic which insures that only one port is selected for access at a time. The multiprocessor system includes a distributed power supply system which insures uninterrupted operation of the remainder of the multiprocessor system in the event of a failure of a power supply for a part of the system. The distributed power supply system includes a separate power supply for each processor module and two separate power supplies for each device controller. Either one of the two power supplies provides the entire power for the device controller in the event the other power supply fails. The distributed power supply system permits any processor module or device controller to be powered down so that on-line maintenance can be performed in a power-off condition while the rest of the multiprocessor system is on-line and functional. The multiprocessor system includes a memory system in which the memory of each processor module is divided into four logical address areas -- user data, system data, user code and system code. The memory system includes a map which translates logical addresses to physical addresses and which coacts with the multiprocessor system to bring pages from secondary memory into primary main memory as required to implement a virtual memory system. The map also provides a protection function. It provides inherent protection among users in a multiprogramming environment, isolates programs from data and protects system programs from the actions of user programs. The map also provides a reference history information for each logical page as an aid to efficient memory management by the operating system. The multiprocessor system includes in the memory of each processor module an error detection and correction system which detects all single bit and double bit errors and which corrects all single bit errors in semiconductor memory storage.

公开(公告)号：DK208383D0

公开(公告)日：1983-05-10

申请号：DK208383

申请日：1983-05-10

Applicant: TANDEM COMPUTERS INC

Inventor： MENZIES PHILIP ROBERT ,  ATWOOD JOHN G JR ,  HINDERS DAVID LEE ,  GREIG DAVID A

IPC: H04M3/00 ,  H04B7/15 ,  H04B7/185 ,  H04B

Abstract: Satellite communications system for computer networks. A multi-node, satellite communications system employing a modified broadcast system is disclosed for use with distributed computer networks. The system involves a plurality of computer systems (network nodes) each capable of transmitting to any other node at a single unique frequency, but capable of receiving from all other nodes simultaneously. Each node in the n-node network comprises a single transmitter with up to n-1 receivers, with each node capable of arbitrating a plurality of requests for transmission access. The invention encompasses a method of communicating digital information in a network of geographically distributed computers.

公开(公告)号：CA1135809A

公开(公告)日：1982-11-16

申请号：CA391314

申请日：1981-12-01

Applicant: TANDEM COMPUTERS INC

Inventor： KATZMAN JAMES A ,  BARTLETT JOEL F ,  BIXLER RICHARD M ,  DAVIDOW WILLIAM H ,  DESPOTAKIS JOHN A ,  GRAZIANO PETER J ,  GREEN MICHAEL D ,  GREIG DAVID A ,  HAYASHI STEVEN J ,  MACKIE DAVID R ,  MCEVOY DENNIS L ,  TREYBIG JAMES G ,  WIERENGA STEVEN W

IPC: H04L5/14

Abstract: A multiprocessor system the kind in which two or more separate processor modules are interconnected for parallel processing includes two redundant interprocessor buses dedicated exclusively to interprocessor communication. Any processor module may send information to any other processor module by either bus. The buses are shared in use by the processor modules on a time-sharing basis. Use of each bus is controlled by a special bus controller. The multiprocessor system includes an input/output system having multi-port device controllers and input/output buses connecting each device controller for access by the input/output channels of at least two different processor modules. Each device controller includes logic which insures that only one port is selected for access at a time. The multiprocessor system includes a distributed power supply system which insures uninterrupted operation of the remainder of the multiprocessor system in the event of a failure of a power supply for a part of the system. The distributed power supply system includes a separate power supply for each processor module and two separate power supplies for each device controller. Either one of the two power supplies provides the entire power for the device controller in the event the other power supply fails. The distributed power supply system permits any processor module or device controller to be powered down so that on-line maintenance can be performed in a power-off condition while the rest of the multiprocessor system is on-line and functional. The multiprocessor system includes a memory system in which the memory of each processor module is divided into four logical address areas -- user data, system data, user code and system code. The memory system includes a map which translates logical addresses to physical addresses and which coacts with the multiprocessor system to bring pages from secondary memory into primary main memory as required to implement a virtual memory system. The map also provides a protection function. It provides inherent protection among users in a multiprogramming environment, isolates programs from data and protects system programs from the actions of user programs. The map also provides a reference history information for each logical page as an aid to efficient memory management by the operating system. The multiprocessor system includes in the memory of each processor module an error detection and correction system which detects all single bit and double bit errors and which corrects all single bit errors in semiconductor memory storage.