公开(公告)号：JPH1153302A

公开(公告)日：1999-02-26

申请号：JP14706898

申请日：1998-05-28

Applicant: TANDEM COMPUTERS INC

Inventor： RAHMAN MIZANUR M ,  SABERNICK FRED C ,  SPROUSE JEFF A ,  GROSZ MARTIN J ,  FU PETER ,  RECTOR RUSSELL M

IPC: G06F15/177 ,  G06F9/445 ,  G06F9/48 ,  G06F11/16 ,  G06F11/20 ,  G06F11/22 ,  G06F12/02 ,  G06F12/08 ,  G06F13/24 ,  G06F13/36 ,  G06F15/16 ,  G06F15/163

Abstract: PROBLEM TO BE SOLVED: To improve an interface to a microprocessor by preparing a logic for intelligently limiting the flow of interrupt information passing through a processor bus between the microprocessor and a processor interface chip. SOLUTION: An interrupt filter 198 is connected to an internal bus interface 182 and a processor bus interface 180 and receives an interrupt signal from an internal bus 26 to send the interrupt given from a 1st class to a processor bus and to store the interrupt given from a 2nd class respectively. The interrupt of the 1st class gives a current effect to a flow of programs of a microprocessor. Meanwhile, the interrupt of the 2nd class gives no effect at all on the current flow of the programs before the stored interrupt affects the flow of the programs.

公开(公告)号：JPH1115687A

公开(公告)日：1999-01-22

申请号：JP14706598

申请日：1998-05-28

Applicant: TANDEM COMPUTERS INC

Inventor： RAHMAN MIZANUR M ,  SABERNICK FRED C ,  SPROUSE JEFF A ,  GROSZ MARTIN J ,  FU PETER ,  RECTOR RUSSELL M

IPC: G06F15/177 ,  G06F9/445 ,  G06F9/48 ,  G06F11/16 ,  G06F11/20 ,  G06F11/22 ,  G06F12/02 ,  G06F12/08 ,  G06F13/24 ,  G06F13/36 ,  G06F15/16 ,  G06F15/163

Abstract: PROBLEM TO BE SOLVED: To obtain an improved interface with respect to a microprocessor by providing a specific address preventing means and an address replacing means. SOLUTION: A boot address locator 194 is provided with a bus input, a bus output and an input for indicating whether the contents of a bus are addresses to be outputted to Ibus. When the contents of a bus are not addresses to be outputted to Ibus, data is put through to the locator 194 without changing data. An AND gate 400 is provided with two inputs, one of them is from a boot exception vector indicator register (BEV-PIC) 218 and the other is an input for indicating whether an input is an address to Ibus. When both of them are true, the AND gate 400 outputs a logic 1 (SELECT = 1) to the selective input of a multiplexer (1...6) to generate the relocation of the address of the bus.

公开(公告)号：JPH10320227A

公开(公告)日：1998-12-04

申请号：JP14706698

申请日：1998-05-28

Applicant: TANDEM COMPUTERS INC

Inventor： RAHMAN MIZANUR M ,  SABERNICK FRED C ,  SPROUSE JEFF A ,  GROSZ MARTIN J ,  FU PETER ,  RECTOR RUSSELL M

IPC: G06F15/177 ,  G06F9/445 ,  G06F9/48 ,  G06F11/16 ,  G06F11/20 ,  G06F11/22 ,  G06F12/02 ,  G06F12/08 ,  G06F13/24 ,  G06F13/36 ,  G06F15/16 ,  G06F15/163

Abstract: PROBLEM TO BE SOLVED: To enable efficient processing while relaxing traffic on a processor bus by intelligently limiting the flow of interruption information through the bus between a microprocessor and a processor interface chip(PIC). SOLUTION: On a PIC 16, a write request is inputted to a register PTAIL 204(1) and write data are collected from a Dbus to a write buffer 208. When the buffer 208 is full, a full/empty flag 209 is set to 'full'. When the prescribed amount of data are loaded to the buffer 208, a controller 206 moves the write request from the PTAIL 204(1) to a register PHEAD 204(2). When an Ibus 26 can be used, the write request is moved there and the full/empty flag 209 is set to 'empty'. Therefore, since the write request or the like is asserted on the PIC 16 only at complete time, the Ibus 26 is efficiently used.

公开(公告)号：JPH10320215A

公开(公告)日：1998-12-04

申请号：JP14706798

申请日：1998-05-28

Applicant: TANDEM COMPUTERS INC

Inventor： RAHMAN MIZANUR M ,  SABERNICK FRED C ,  SPROUSE JEFF A ,  GROSZ MARTIN J ,  FU PETER ,  RECTOR RUSSELL M

IPC: G06F15/177 ,  G06F9/445 ,  G06F9/48 ,  G06F11/16 ,  G06F11/20 ,  G06F11/22 ,  G06F12/02 ,  G06F12/08 ,  G06F13/24 ,  G06F13/36 ,  G06F9/46 ,  G06F15/16 ,  G06F15/163

Abstract: PROBLEM TO BE SOLVED: To prevent a processor system from being destroyed by the operation of external circuit by intelligently limiting the flow of interruption information between a microprocessor and an interface chip. SOLUTION: Interruptions received through an Ibus 26 are stored in a register 460 based on their interruption numbers. In case of certain interruption, a value passed together with its interruption number is stored together with the setting instruction of interruption in set or reset state and based on a priority mechanism, the priority is determined. An interruption image register 452 maintains the copy of object to exist in an interruption register 450 at a microprocessor 12. The register 452 is updated by the output of master 466 to an internal bus 490, reserve update contents in the register 452 are compared with contents on the internal bus 490 by a comparator 470 and in order to update the register 450, the quantity of traffic on a Pbus 18 is decreased.

公开(公告)号：CA2127081A1

公开(公告)日：1995-01-07

申请号：CA2127081

申请日：1994-06-29

Applicant: TANDEM COMPUTERS INC

Inventor： RAHMAN MIZANUR M ,  SABERNICK FRED C ,  SPROUSE JEFF A ,  GROSZ MARTIN J ,  FU PETER ,  RECTOR RUSSELL M

IPC: G06F15/177 ,  G06F9/445 ,  G06F9/48 ,  G06F11/16 ,  G06F11/20 ,  G06F11/22 ,  G06F12/02 ,  G06F12/08 ,  G06F13/24 ,  G06F13/36 ,  G06F15/80

Abstract: PROCESSOR INTERFACE CHIP FOR DUAL-MICROPROCESSOR PROCESSOR SYSTEM A processor interface chip and a maintenance diagnostic chip are provided coupled with two microprocessors designed to be run in tandem. The processor interface chip includes logic for interfacing between the microprocessors and a main memory, logic for pipelining multiple microprocessor requests between the microprocessors and main memory, logic for prefetching data before a microprocessor issues a read request, logic for allowing a boot to occur from code anywhere in physical memory without regard to the microprocessors' fixed memory location for boot code, and logic for intelligently limiting the flow of interrupt information over a processor bus between the microprocessors and the processor interface chip. The maintenance diagnostic chip includes logic to halt either of the microprocessors if an error is detected, and read out the state of the microprocessors and a secondary cache attached to the microprocessors, before the state of the microprocessors at the time of the fault changes to a different state which might hide evidence of the cause of the fault.