公开(公告)号：JPH07170174A

公开(公告)日：1995-07-04

申请号：JP15073694

申请日：1994-07-01

Applicant: TANDEM COMPUTERS INC

Inventor： RATSUSERU ENU MIRO ,  DEYUUKU GAKU RE ,  FURANKU MIKARAUSUKASU ,  SHII JIYON GUREEBENKENPAA ,  KININGU KUWAN

IPC: G06F1/12 ,  G06F1/06 ,  G06F11/16 ,  H03K5/15 ,  H03L7/00

Abstract: PURPOSE: To ensure the proper operation of a system by generating plural frequency clock signals, generating an error signal when incoincidence is detected between the clocks, and re-setting a clock generating means to a prescribed state in response to the error signal. CONSTITUTION: A clock generator system 10 is provided with an error detecting logic, and receives 25 output clock signals from a master clock generating unit 12a and 25 output clocks from a shadow clock generating unit 12b. The error detecting logic compares the output signal of the unit 12a with the corresponding signal of the unit 12b, and outputs an ERROR signal when incoincidence is detected. Next, a reset logic 32 generates a reset signal, and connects a frequency divider 30 of the units 12a and 12b so that they can be reset to the same reset state, re-started, and restored from the error.

公开(公告)号：JPH07168645A

公开(公告)日：1995-07-04

申请号：JP14900294

申请日：1994-06-30

Applicant: TANDEM COMPUTERS INC

Inventor： RINDA WAI ITSUPU ,  KININGU KUWAN

IPC: G06F1/10

Abstract: PURPOSE: To limit clock skew generated in clock signals as much as possible and to distribute the clock signals on an integrated circuit chip by receiving the clock signals by an input terminal and transmitting them to a straight route and a closed loop route. CONSTITUTION: The integrated circuit chip 12a receives the clock signals transmitted by a clock bus 16 by an input pad 20. The input pad 20 is connected through pre-driver circuits 26a and 26b to the respectively two sets of driver circuits 28a and 30a and 28b and 30b. The driver circuit 28 is provided with a pair of drivers parallelly connected to the end part 33 of the straight route 36 formed at the center of the chip 12a. The driver circuit 30 is connected to the closed loop route 34 at points positioned on the opposite side of each other. The closed loop route 34 is formed near the periphery of the chip 12a. The clock input of an I/O device is connected to the closed loop route 34 by branching connection 35 and the clock input of an internal device is connected to the straight route 36 by the branching connection 37.