公开(公告)号：JPH07170174A

公开(公告)日：1995-07-04

申请号：JP15073694

申请日：1994-07-01

Applicant: TANDEM COMPUTERS INC

Inventor： RATSUSERU ENU MIRO ,  DEYUUKU GAKU RE ,  FURANKU MIKARAUSUKASU ,  SHII JIYON GUREEBENKENPAA ,  KININGU KUWAN

IPC: G06F1/12 ,  G06F1/06 ,  G06F11/16 ,  H03K5/15 ,  H03L7/00

Abstract: PURPOSE: To ensure the proper operation of a system by generating plural frequency clock signals, generating an error signal when incoincidence is detected between the clocks, and re-setting a clock generating means to a prescribed state in response to the error signal. CONSTITUTION: A clock generator system 10 is provided with an error detecting logic, and receives 25 output clock signals from a master clock generating unit 12a and 25 output clocks from a shadow clock generating unit 12b. The error detecting logic compares the output signal of the unit 12a with the corresponding signal of the unit 12b, and outputs an ERROR signal when incoincidence is detected. Next, a reset logic 32 generates a reset signal, and connects a frequency divider 30 of the units 12a and 12b so that they can be reset to the same reset state, re-started, and restored from the error.