公开(公告)号：JPH10336019A

公开(公告)日：1998-12-18

申请号：JP9348898

申请日：1998-04-06

Applicant: TANDEM COMPUTERS INC

Inventor： MIROV RUSSELL N ,  LE DUC NGOC ,  MIKALAUSKAS FRANK ,  GREBENKEMPER C JOHN ,  KWAN KINYING

IPC: G06F1/12 ,  G06F1/06 ,  G06F11/16 ,  H03K5/15 ,  H03L7/00

Abstract: PROBLEM TO BE SOLVED: To obtain clock generator system that generates many clock signals having different frequencies by providing a pair of clock generating units of substantially the same configuration. SOLUTION: A pair of clock generating units of substantially the same configuration 12a (master) and 12b (shadow) are provided. The configuration of the two units 12a and 12b is substantially the same and for example, the master unit 12a receives a clock signal (by way of a buffer 22) being the product of a clock oscillator 20 to input receiving circuits 16 and 18. The circuit 16 directly receives the clock and forms EARLY CLK from there. On the other hand, the circuit 18 receives a clock signal, which is delayed to three nanosecond by a (variable) delay line 24 in spite of the same clock signal and forms a clock signal ON TIME CLOCK from there.

公开(公告)号：DE69403028D1

公开(公告)日：1997-06-12

申请号：DE69403028

申请日：1994-06-27

Applicant: TANDEM COMPUTERS INC

Inventor： YIP LINDA Y ,  KWAN KINYING

IPC: G06F1/10

Abstract: A master clock signal, used to.operate the clock devices (e.g., flip flops) formed on an integrated circuit chip, includes first and second clock paths. The first clock path is a linear trunk having laterally extending tributaries. The clock trunk is driven, through buffer circuits, at both ends with the master clock, and the internal devices coupled to the tributaries to receive the clock signal. The second path comprises a closed loop formed proximate the periphery of the integrated circuit chip. Clock buffer circuitry receives the master clock signal and apply that master clock signal to two points on the closed loop path. The closed loop path is used to communicate the master clock to only the input/output devices, i.e., those that receive data and/or informational signals from an external source, or those communicate such signals to a destination external to the integrated circuit.

公开(公告)号：AU667781B2

公开(公告)日：1996-04-04

申请号：AU6614994

申请日：1994-07-01

Applicant: TANDEM COMPUTERS INC

Inventor： YIP LINDA Y ,  KWAN KINYING

IPC: G06F1/10

Abstract: A master clock signal, used to.operate the clock devices (e.g., flip flops) formed on an integrated circuit chip, includes first and second clock paths. The first clock path is a linear trunk having laterally extending tributaries. The clock trunk is driven, through buffer circuits, at both ends with the master clock, and the internal devices coupled to the tributaries to receive the clock signal. The second path comprises a closed loop formed proximate the periphery of the integrated circuit chip. Clock buffer circuitry receives the master clock signal and apply that master clock signal to two points on the closed loop path. The closed loop path is used to communicate the master clock to only the input/output devices, i.e., those that receive data and/or informational signals from an external source, or those communicate such signals to a destination external to the integrated circuit.

公开(公告)号：CA2126622A1

公开(公告)日：1995-01-03

申请号：CA2126622

申请日：1994-06-23

Applicant: TANDEM COMPUTERS INC

Inventor： YIP LINDA Y ,  KWAN KINYING

IPC: G06F1/10 ,  H01L23/64 ,  H01L23/498 ,  H01L23/50 ,  H01L23/66

Abstract: ON CHIP CLOCK SKEW CONTROL METHOD AND APPARATUS A master clock signal, used to operate the clock devices (e.g., flip flops) formed on an integrated circuit chip, includes first and second clock paths. The first clock path is a linear trunk having laterally extending tributaries. The clock trunk is driven, through buffer circuits, at both ends with the master clock, and the internal devices coupled to the tributaries to receive the clock signal. The second path comprises a closed loop formed proximate the periphery of the integrated circuit chip. Clock buffer circuitry receives the master clock signal and apply that master clock signal to two points on the closed loop path. The closed loop path is used to communicate the master clock to only the input/output devices, i.e., those that receive data and/or informational signals from an external source, or those communicate such signals to a destination external to the integrated circuit.

公开(公告)号：DE69415090D1

公开(公告)日：1999-01-21

申请号：DE69415090

申请日：1994-06-20

Applicant: TANDEM COMPUTERS INC

Inventor： MIROV RUSSELL N ,  LE DUC NGOC ,  MIKALAUSKAS FRANK ,  GREBENKEMPER C JOHN ,  KWAN KINYING

IPC: G06F1/12 ,  G06F1/06 ,  G06F11/16 ,  H03K5/15 ,  H03L7/00 ,  G06F11/00 ,  G06F1/10

Abstract: A clock generator system includes two separate, similarly structured clock generator units, operating in lock-step unison, and with the digital clock signal outputs of one of the generator units distributed to the sync, clocked devices and to an error detection circuit, that also receives the digital clock signals from the other clock generator unit for comparison with one another. In the event an error being detected, an error detection circuit produces an error signal to halt operation of the system with which the clock generator system is used, and to reset the clock generator.

公开(公告)号：AU684436B2

公开(公告)日：1997-12-11

申请号：AU7052696

申请日：1996-10-31

Applicant: TANDEM COMPUTERS INC

Inventor： MIROV RUSSELL N ,  LE DUC NGOC ,  MIKALAUSKAS FRANK ,  GREBENKEMPER C JOHN ,  KWAN KINYING

IPC: G06F1/12 ,  G06F1/06 ,  G06F11/16 ,  H03K5/15 ,  H03L7/00 ,  H03H5/00 ,  H03L7/24

Abstract: A clock generator system includes two separate, similarly structured clock generator units, operating in lock-step unison, and with the digital clock signal outputs of one of the generator units distributed to the sync, clocked devices and to an error detection circuit, that also receives the digital clock signals from the other clock generator unit for comparison with one another. In the event an error being detected, an error detection circuit produces an error signal to halt operation of the system with which the clock generator system is used, and to reset the clock generator.

公开(公告)号：AU674579B2

公开(公告)日：1997-01-02

申请号：AU6614894

申请日：1994-07-01

Applicant: TANDEM COMPUTERS INC

Inventor： MIROV RUSSELL N ,  KWAN KINYING ,  GREBENKEMPER C JOHN ,  MIKALAUSKAS FRANK ,  LE DUC NGOC

IPC: G06F1/12 ,  G06F1/06 ,  G06F11/16 ,  H03K5/15 ,  H03L7/00 ,  H03L7/24

Abstract: A clock generator system includes two separate, similarly structured clock generator units, operating in lock-step unison, and with the digital clock signal outputs of one of the generator units distributed to the sync, clocked devices and to an error detection circuit, that also receives the digital clock signals from the other clock generator unit for comparison with one another. In the event an error being detected, an error detection circuit produces an error signal to halt operation of the system with which the clock generator system is used, and to reset the clock generator.

公开(公告)号：CA2124746A1

公开(公告)日：1995-01-03

申请号：CA2124746

申请日：1994-05-31

Applicant: TANDEM COMPUTERS INC

Inventor： MIROV RUSSELL N ,  LE DUC N ,  MIKALAUSKAS FRANK ,  GREBENKEMPER C JOHN ,  KWAN KINYING

IPC: G06F1/12 ,  G06F1/06 ,  G06F11/16 ,  H03K5/15 ,  H03L7/00 ,  H03K3/02

Abstract: 23 MULTIPLE FREQUENCY OUTPUT CLOCK GENERATOR SYSTEM A clock generator system for producing a number of multiple frequency digital clock signals for distribution to a number of synchronous, clocked devices, include two separate, substantially identically structured clock generator units that operate in lock-step unison. The digital clock signal outputs of one of the generator units is distributed to the synchronous, clocked devices and to a error detection circuit, that also receives the digital clock signals from other clock generator unite for comparison with one another. In the event an error is detected, the error detection circuit will produce an error signal to halt operation of the system with which the clock generator system is used, and reset the clock generator.

公开(公告)号：DE69415090T2

公开(公告)日：1999-05-20

申请号：DE69415090

申请日：1994-06-20

Applicant: TANDEM COMPUTERS INC

Inventor： MIROV RUSSELL N ,  LE DUC NGOC ,  MIKALAUSKAS FRANK ,  GREBENKEMPER C JOHN ,  KWAN KINYING

IPC: G06F1/12 ,  G06F1/06 ,  G06F11/16 ,  H03K5/15 ,  H03L7/00 ,  G06F11/00 ,  G06F1/10

Abstract: A clock generator system includes two separate, similarly structured clock generator units, operating in lock-step unison, and with the digital clock signal outputs of one of the generator units distributed to the sync, clocked devices and to an error detection circuit, that also receives the digital clock signals from the other clock generator unit for comparison with one another. In the event an error being detected, an error detection circuit produces an error signal to halt operation of the system with which the clock generator system is used, and to reset the clock generator.

公开(公告)号：DE69403028T2

公开(公告)日：1997-09-25

申请号：DE69403028

申请日：1994-06-27

Applicant: TANDEM COMPUTERS INC

Inventor： YIP LINDA Y ,  KWAN KINYING

IPC: G06F1/10

Abstract: A master clock signal, used to.operate the clock devices (e.g., flip flops) formed on an integrated circuit chip, includes first and second clock paths. The first clock path is a linear trunk having laterally extending tributaries. The clock trunk is driven, through buffer circuits, at both ends with the master clock, and the internal devices coupled to the tributaries to receive the clock signal. The second path comprises a closed loop formed proximate the periphery of the integrated circuit chip. Clock buffer circuitry receives the master clock signal and apply that master clock signal to two points on the closed loop path. The closed loop path is used to communicate the master clock to only the input/output devices, i.e., those that receive data and/or informational signals from an external source, or those communicate such signals to a destination external to the integrated circuit.