公开(公告)号：JPS6231441A

公开(公告)日：1987-02-10

申请号：JP10753686

申请日：1986-05-10

Applicant: TANDEM COMPUTERS INC

Inventor： CHANDRAN SRIKUMAR R ,  WALKER MARK S ,  RHODES EDWARD J ,  LUI ALBERT S

IPC: G06F11/18 ,  G06F11/00 ,  G06F11/10 ,  G06F11/16 ,  G06F13/12 ,  G06F13/28

公开(公告)号：NO861863L

公开(公告)日：1986-11-11

申请号：NO861863

申请日：1986-05-09

Applicant: TANDEM COMPUTERS INC

Inventor： CHANDRAN SRIKUMAR R ,  WALKER MARK S ,  RHODES EDWARD J ,  LUI ALBERT S

IPC: G06F11/00 ,  G06F11/18 ,  G06F11/10 ,  G06F11/16 ,  G06F13/12 ,  G06F13/28 ,  G06F

Abstract: The present invention is an input/output controller for providing total data integrity for any single point failure. The I/O controller comprises a processor module having two microprocessors, an associated memory, a direct memory access module ( >), and a processor support module ( >); a device drive interface; and a channel interface. The two microprocessors are operated in lockstep as a dual modular redundant processor system. The processors provide true and complement, respectively, addresses, data and control strobes. The PSM compares the true and complement data to detect errors (i.e., corresponding data bits not being a true-complement pair) and generates parity protected data (and checks parity) on the data bus. The PSM also generates and checks dual railed control strobes and provides synchronization of all control strobes and interrupt signals to enable the true-complement pair of microprocessors to operate in lock-step. The DMA compares the redundant addresses from the processors to detect errors and to generate parity protected addresses (and check parity) on the address bus. The DMA also generates and checks bus arbitration signals and controls direct memory access. Self-checking checkers are used to check the various dual railed, true-complement pairs of signals to detect, locate and isolate faults. Miscompares between true-complement address, data and control signals and parity errors detected in reading program instructions from memory all are treated as fatal errors, which cause both processors to halt. Other types of errors are treated as nonfatal, which cause processor exceptions during which appropriate programming is executed to locate and isolate such errors.

公开(公告)号：AU568977B2

公开(公告)日：1988-01-14

申请号：AU5720486

申请日：1986-05-07

Applicant: TANDEM COMPUTERS INC

Inventor： CHANDRAN SRIKUMAR R ,  WALKER MARK S ,  RHODES EDWARD J ,  LUI ALBERT S

IPC: G06F11/18 ,  G06F11/00 ,  G06F11/10 ,  G06F11/16 ,  G06F13/12 ,  G06F13/28 ,  G06F11/08 ,  G06F15/16

Abstract: The present invention is an input/output controller for providing total data integrity for any single point failure. The I/O controller comprises a processor module having two microprocessors, an associated memory, a direct memory access module ( >), and a processor support module ( >); a device drive interface; and a channel interface. The two microprocessors are operated in lockstep as a dual modular redundant processor system. The processors provide true and complement, respectively, addresses, data and control strobes. The PSM compares the true and complement data to detect errors (i.e., corresponding data bits not being a true-complement pair) and generates parity protected data (and checks parity) on the data bus. The PSM also generates and checks dual railed control strobes and provides synchronization of all control strobes and interrupt signals to enable the true-complement pair of microprocessors to operate in lock-step. The DMA compares the redundant addresses from the processors to detect errors and to generate parity protected addresses (and check parity) on the address bus. The DMA also generates and checks bus arbitration signals and controls direct memory access. Self-checking checkers are used to check the various dual railed, true-complement pairs of signals to detect, locate and isolate faults. Miscompares between true-complement address, data and control signals and parity errors detected in reading program instructions from memory all are treated as fatal errors, which cause both processors to halt. Other types of errors are treated as nonfatal, which cause processor exceptions during which appropriate programming is executed to locate and isolate such errors.

公开(公告)号：DE3686901T2

公开(公告)日：1993-02-18

申请号：DE3686901

申请日：1986-05-09

Applicant: TANDEM COMPUTERS INC

Inventor： CHANDRAN SRIKUMAR R ,  WALKER MARK S ,  RHODES EDWARD J ,  LUI ALBERT S

IPC: G06F11/18 ,  G06F11/00 ,  G06F11/10 ,  G06F11/16 ,  G06F13/12 ,  G06F13/28

Abstract: The present invention is an input/output controller for providing total data integrity for any single point failure. The I/O controller comprises a processor module having two microprocessors, an associated memory, a direct memory access module ( >), and a processor support module ( >); a device drive interface; and a channel interface. The two microprocessors are operated in lockstep as a dual modular redundant processor system. The processors provide true and complement, respectively, addresses, data and control strobes. The PSM compares the true and complement data to detect errors (i.e., corresponding data bits not being a true-complement pair) and generates parity protected data (and checks parity) on the data bus. The PSM also generates and checks dual railed control strobes and provides synchronization of all control strobes and interrupt signals to enable the true-complement pair of microprocessors to operate in lock-step. The DMA compares the redundant addresses from the processors to detect errors and to generate parity protected addresses (and check parity) on the address bus. The DMA also generates and checks bus arbitration signals and controls direct memory access. Self-checking checkers are used to check the various dual railed, true-complement pairs of signals to detect, locate and isolate faults. Miscompares between true-complement address, data and control signals and parity errors detected in reading program instructions from memory all are treated as fatal errors, which cause both processors to halt. Other types of errors are treated as nonfatal, which cause processor exceptions during which appropriate programming is executed to locate and isolate such errors.

公开(公告)号：DE3686901D1

公开(公告)日：1992-11-12

申请号：DE3686901

申请日：1986-05-09

Applicant: TANDEM COMPUTERS INC

Inventor： CHANDRAN SRIKUMAR R ,  WALKER MARK S ,  RHODES EDWARD J ,  LUI ALBERT S

IPC: G06F11/18 ,  G06F11/00 ,  G06F11/10 ,  G06F11/16 ,  G06F13/12 ,  G06F13/28

Abstract: The present invention is an input/output controller for providing total data integrity for any single point failure. The I/O controller comprises a processor module having two microprocessors, an associated memory, a direct memory access module ( >), and a processor support module ( >); a device drive interface; and a channel interface. The two microprocessors are operated in lockstep as a dual modular redundant processor system. The processors provide true and complement, respectively, addresses, data and control strobes. The PSM compares the true and complement data to detect errors (i.e., corresponding data bits not being a true-complement pair) and generates parity protected data (and checks parity) on the data bus. The PSM also generates and checks dual railed control strobes and provides synchronization of all control strobes and interrupt signals to enable the true-complement pair of microprocessors to operate in lock-step. The DMA compares the redundant addresses from the processors to detect errors and to generate parity protected addresses (and check parity) on the address bus. The DMA also generates and checks bus arbitration signals and controls direct memory access. Self-checking checkers are used to check the various dual railed, true-complement pairs of signals to detect, locate and isolate faults. Miscompares between true-complement address, data and control signals and parity errors detected in reading program instructions from memory all are treated as fatal errors, which cause both processors to halt. Other types of errors are treated as nonfatal, which cause processor exceptions during which appropriate programming is executed to locate and isolate such errors.

公开(公告)号：AT81412T

公开(公告)日：1992-10-15

申请号：AT86303566

申请日：1986-05-09

Applicant: TANDEM COMPUTERS INC

Inventor： CHANDRAN SRIKUMAR R ,  WALKER MARK S ,  RHODES EDWARD J ,  LUI ALBERT S

IPC: G06F11/18 ,  G06F11/00 ,  G06F11/10 ,  G06F11/16 ,  G06F13/12 ,  G06F13/28

Abstract: The present invention is an input/output controller for providing total data integrity for any single point failure. The I/O controller comprises a processor module having two microprocessors, an associated memory, a direct memory access module ( >), and a processor support module ( >); a device drive interface; and a channel interface. The two microprocessors are operated in lockstep as a dual modular redundant processor system. The processors provide true and complement, respectively, addresses, data and control strobes. The PSM compares the true and complement data to detect errors (i.e., corresponding data bits not being a true-complement pair) and generates parity protected data (and checks parity) on the data bus. The PSM also generates and checks dual railed control strobes and provides synchronization of all control strobes and interrupt signals to enable the true-complement pair of microprocessors to operate in lock-step. The DMA compares the redundant addresses from the processors to detect errors and to generate parity protected addresses (and check parity) on the address bus. The DMA also generates and checks bus arbitration signals and controls direct memory access. Self-checking checkers are used to check the various dual railed, true-complement pairs of signals to detect, locate and isolate faults. Miscompares between true-complement address, data and control signals and parity errors detected in reading program instructions from memory all are treated as fatal errors, which cause both processors to halt. Other types of errors are treated as nonfatal, which cause processor exceptions during which appropriate programming is executed to locate and isolate such errors.

公开(公告)号：AU5720486A

公开(公告)日：1986-11-13

申请号：AU5720486

申请日：1986-05-07

Applicant: TANDEM COMPUTERS INC

Inventor： CHANDRAN SRIKUMAR R ,  WALKER MARK S ,  RHODES EDWARD J ,  LUI ALBERT S

IPC: G06F11/18 ,  G06F11/00 ,  G06F11/10 ,  G06F11/16 ,  G06F13/12 ,  G06F13/28

Abstract: The present invention is an input/output controller for providing total data integrity for any single point failure. The I/O controller comprises a processor module having two microprocessors, an associated memory, a direct memory access module ( >), and a processor support module ( >); a device drive interface; and a channel interface. The two microprocessors are operated in lockstep as a dual modular redundant processor system. The processors provide true and complement, respectively, addresses, data and control strobes. The PSM compares the true and complement data to detect errors (i.e., corresponding data bits not being a true-complement pair) and generates parity protected data (and checks parity) on the data bus. The PSM also generates and checks dual railed control strobes and provides synchronization of all control strobes and interrupt signals to enable the true-complement pair of microprocessors to operate in lock-step. The DMA compares the redundant addresses from the processors to detect errors and to generate parity protected addresses (and check parity) on the address bus. The DMA also generates and checks bus arbitration signals and controls direct memory access. Self-checking checkers are used to check the various dual railed, true-complement pairs of signals to detect, locate and isolate faults. Miscompares between true-complement address, data and control signals and parity errors detected in reading program instructions from memory all are treated as fatal errors, which cause both processors to halt. Other types of errors are treated as nonfatal, which cause processor exceptions during which appropriate programming is executed to locate and isolate such errors.

公开(公告)号：NO174406C

公开(公告)日：1994-04-27

申请号：NO861863

申请日：1986-05-09

Applicant: TANDEM COMPUTERS INC

Inventor： CHANDRAN SRIKUMAR R ,  WALKER MARK S ,  RHODES EDWARD J ,  LUI ALBERT S

IPC: G06F11/00 ,  G06F11/10 ,  G06F11/16 ,  G06F11/18 ,  G06F13/12 ,  G06F13/28 ,  G06F12/02

Abstract: The present invention is an input/output controller for providing total data integrity for any single point failure. The I/O controller comprises a processor module having two microprocessors, an associated memory, a direct memory access module ( >), and a processor support module ( >); a device drive interface; and a channel interface. The two microprocessors are operated in lockstep as a dual modular redundant processor system. The processors provide true and complement, respectively, addresses, data and control strobes. The PSM compares the true and complement data to detect errors (i.e., corresponding data bits not being a true-complement pair) and generates parity protected data (and checks parity) on the data bus. The PSM also generates and checks dual railed control strobes and provides synchronization of all control strobes and interrupt signals to enable the true-complement pair of microprocessors to operate in lock-step. The DMA compares the redundant addresses from the processors to detect errors and to generate parity protected addresses (and check parity) on the address bus. The DMA also generates and checks bus arbitration signals and controls direct memory access. Self-checking checkers are used to check the various dual railed, true-complement pairs of signals to detect, locate and isolate faults. Miscompares between true-complement address, data and control signals and parity errors detected in reading program instructions from memory all are treated as fatal errors, which cause both processors to halt. Other types of errors are treated as nonfatal, which cause processor exceptions during which appropriate programming is executed to locate and isolate such errors.

公开(公告)号：NO174406B

公开(公告)日：1994-01-17

申请号：NO861863

申请日：1986-05-09

Applicant: TANDEM COMPUTERS INC

Inventor： CHANDRAN SRIKUMAR R ,  WALKER MARK S ,  RHODES EDWARD J ,  LUI ALBERT S

IPC: G06F11/00 ,  G06F11/10 ,  G06F11/16 ,  G06F11/18 ,  G06F13/12 ,  G06F13/28 ,  G06F12/02

Abstract: The present invention is an input/output controller for providing total data integrity for any single point failure. The I/O controller comprises a processor module having two microprocessors, an associated memory, a direct memory access module ( >), and a processor support module ( >); a device drive interface; and a channel interface. The two microprocessors are operated in lockstep as a dual modular redundant processor system. The processors provide true and complement, respectively, addresses, data and control strobes. The PSM compares the true and complement data to detect errors (i.e., corresponding data bits not being a true-complement pair) and generates parity protected data (and checks parity) on the data bus. The PSM also generates and checks dual railed control strobes and provides synchronization of all control strobes and interrupt signals to enable the true-complement pair of microprocessors to operate in lock-step. The DMA compares the redundant addresses from the processors to detect errors and to generate parity protected addresses (and check parity) on the address bus. The DMA also generates and checks bus arbitration signals and controls direct memory access. Self-checking checkers are used to check the various dual railed, true-complement pairs of signals to detect, locate and isolate faults. Miscompares between true-complement address, data and control signals and parity errors detected in reading program instructions from memory all are treated as fatal errors, which cause both processors to halt. Other types of errors are treated as nonfatal, which cause processor exceptions during which appropriate programming is executed to locate and isolate such errors.

公开(公告)号：CA1259415A

公开(公告)日：1989-09-12

申请号：CA508762

申请日：1986-05-09

Applicant: TANDEM COMPUTERS INC

Inventor： CHANDRAN SRIKUMAR R ,  WALKER MARK S ,  RHODES EDWARD J ,  LUI ALBERT S

IPC: G06F11/18 ,  G06F11/00 ,  G06F11/10 ,  G06F11/16 ,  G06F13/12 ,  G06F13/28

Abstract: HIGH LEVEL SELF-CHECKING INTELLIGENT I/O CONTROLLER The present invention is an input/output controller for providing total data integrity for any single point failure. The I/O controller comprises a processor module having two microprocessors, an associated memory, a direct memory access module ("DMA"), and a processor support module ("PSM"); a device drive interface; and a channel interface. The two microprocessors are operated in lockstep as a dual modular redundant processor system. The processors provide true and complement, respectively, addresses, data and control strobes. The PSM compares the true and complement data to detect errors (i.e., corresponding data bits not being a true-complement pair) and generates parity protected data (and checks parity) on the data bus. The PSM also generates and checks dual railed control strobes and provides synchronization of all control strobes and interrupt signals to enable the true-complement pair of microprocessors to operate in lockstep. The DMA compares the redundant addresses from the processors to detect errors and to generate parity protected addresses (and check parity) on the address bus. The DMA also generates and checks bus arbitration signals and controls direct memory access. Self-checking checkers are used to check the various dual railed, true-complement pairs of signals to detect, locate and isolate internal faults. Miscompares between true-complement address, data and control signals and parity errors detected in reading program instructions from memory all are -treated as fatal errors, which cause both processors to halt. Other types of errors are treated as nonfatal, which cause processor exceptions during which appropriate programming is executed to locate and isolate such errors.