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公开(公告)号：JPS6231440A
公开(公告)日：1987-02-10
申请号：JP10652786
申请日：1986-05-09
Applicant: TANDEM COMPUTERS INC
Inventor： CHANDRAN SRIKUMAR R , WALKER MARK S
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公开(公告)号：JPS6231441A
公开(公告)日：1987-02-10
申请号：JP10753686
申请日：1986-05-10
Applicant: TANDEM COMPUTERS INC
Inventor： CHANDRAN SRIKUMAR R , WALKER MARK S , RHODES EDWARD J , LUI ALBERT S
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公开(公告)号：CA1253926A
公开(公告)日：1989-05-09
申请号：CA508763
申请日：1986-05-09
Applicant: TANDEM COMPUTERS INC
Inventor： CHANDRAN SRIKUMAR R , WALKER MARK S
Abstract: SELF-CHECKING, DUAL RAILED, LEADING EDGE SYNCHRONIZER The present invention relates to a digital logic circuit and method for synchronizing the leading edges of a skewed true-complement signal pair. The circuit of the present invention is comprised of two similar, interconnected circuit halves, each of which includes three D flip-flop stages. The outputs from the second D flip-flop stages from the two circuit halves are applied to the two inputs of two identical logic gates, such that the signal pair is synchronously transmitted to a pair of output gates through a third D flip-flop stage in each circuit half. The second D flip-flop stages also prevent metastable states from reaching the synchronizer output. Metastable states may result if the input setup time is violated for the first D flip-flop stages. The third D flip-flop stage in each circuit half also eliminates any signal irregularities generated in the logic circuitry from appearing on the synchronizer output lines. The present invention is self-checking in that any single fault in the input signals or in the synchronizer circuit itself will result in the synchronizer output pair not having a true complement relationship.
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公开(公告)号：NO861863L
公开(公告)日：1986-11-11
申请号：NO861863
申请日：1986-05-09
Applicant: TANDEM COMPUTERS INC
Inventor： CHANDRAN SRIKUMAR R , WALKER MARK S , RHODES EDWARD J , LUI ALBERT S
Abstract: The present invention is an input/output controller for providing total data integrity for any single point failure. The I/O controller comprises a processor module having two microprocessors, an associated memory, a direct memory access module ( >), and a processor support module ( >); a device drive interface; and a channel interface. The two microprocessors are operated in lockstep as a dual modular redundant processor system. The processors provide true and complement, respectively, addresses, data and control strobes. The PSM compares the true and complement data to detect errors (i.e., corresponding data bits not being a true-complement pair) and generates parity protected data (and checks parity) on the data bus. The PSM also generates and checks dual railed control strobes and provides synchronization of all control strobes and interrupt signals to enable the true-complement pair of microprocessors to operate in lock-step. The DMA compares the redundant addresses from the processors to detect errors and to generate parity protected addresses (and check parity) on the address bus. The DMA also generates and checks bus arbitration signals and controls direct memory access. Self-checking checkers are used to check the various dual railed, true-complement pairs of signals to detect, locate and isolate faults. Miscompares between true-complement address, data and control signals and parity errors detected in reading program instructions from memory all are treated as fatal errors, which cause both processors to halt. Other types of errors are treated as nonfatal, which cause processor exceptions during which appropriate programming is executed to locate and isolate such errors.
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公开(公告)号：DE3686902T2
公开(公告)日：1993-02-18
申请号：DE3686902
申请日：1986-05-09
Applicant: TANDEM COMPUTERS INC
Inventor： CHANDRAN SRIKUMAR R , WALKER MARK S
Abstract: The present invention relates to a digital logic circuit and method for synchronizing the leading edges of a skewed true-complement signal pair. The circuit of the present invention is comprised of two similar, interconnected circuit halves, each of which includes three D flip-flop stages. The outputs from the second D flip-flop stages from the two circuit halves are applied to the two inputs of two identical logic gates, such that the signal pair is synchronously transmitted to a pair of output gates through a third D flip-flop stage in each circuit half. The second D flip-flop stages also prevent metastable states from reaching the synchronizer output. Metastable states may result if the input setup time is violated for the first D flip-flop stages. The third D flip-flop stage in each circuit half also eliminates any signal irregularities generated in the logic circuitry from appearing on the synchronizer output lines. The present invention is self-checking in that any single fault in the input signals or in the synchronizer circuit itself will result in the synchronizer output pair not having a true complement relationship.
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Patent Agency Ranking
公开(公告)号：AT81427T
公开(公告)日：1992-10-15
申请号：AT86303561
申请日：1986-05-09
Applicant: TANDEM COMPUTERS INC
Inventor： CHANDRAN SRIKUMAR R , WALKER MARK S
Abstract: The present invention relates to a digital logic circuit and method for synchronizing the leading edges of a skewed true-complement signal pair. The circuit of the present invention is comprised of two similar, interconnected circuit halves, each of which includes three D flip-flop stages. The outputs from the second D flip-flop stages from the two circuit halves are applied to the two inputs of two identical logic gates, such that the signal pair is synchronously transmitted to a pair of output gates through a third D flip-flop stage in each circuit half. The second D flip-flop stages also prevent metastable states from reaching the synchronizer output. Metastable states may result if the input setup time is violated for the first D flip-flop stages. The third D flip-flop stage in each circuit half also eliminates any signal irregularities generated in the logic circuitry from appearing on the synchronizer output lines. The present invention is self-checking in that any single fault in the input signals or in the synchronizer circuit itself will result in the synchronizer output pair not having a true complement relationship.
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公开(公告)号：AU568977B2
公开(公告)日：1988-01-14
申请号：AU5720486
申请日：1986-05-07
Applicant: TANDEM COMPUTERS INC
Inventor： CHANDRAN SRIKUMAR R , WALKER MARK S , RHODES EDWARD J , LUI ALBERT S
Abstract: The present invention is an input/output controller for providing total data integrity for any single point failure. The I/O controller comprises a processor module having two microprocessors, an associated memory, a direct memory access module ( >), and a processor support module ( >); a device drive interface; and a channel interface. The two microprocessors are operated in lockstep as a dual modular redundant processor system. The processors provide true and complement, respectively, addresses, data and control strobes. The PSM compares the true and complement data to detect errors (i.e., corresponding data bits not being a true-complement pair) and generates parity protected data (and checks parity) on the data bus. The PSM also generates and checks dual railed control strobes and provides synchronization of all control strobes and interrupt signals to enable the true-complement pair of microprocessors to operate in lock-step. The DMA compares the redundant addresses from the processors to detect errors and to generate parity protected addresses (and check parity) on the address bus. The DMA also generates and checks bus arbitration signals and controls direct memory access. Self-checking checkers are used to check the various dual railed, true-complement pairs of signals to detect, locate and isolate faults. Miscompares between true-complement address, data and control signals and parity errors detected in reading program instructions from memory all are treated as fatal errors, which cause both processors to halt. Other types of errors are treated as nonfatal, which cause processor exceptions during which appropriate programming is executed to locate and isolate such errors.
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公开(公告)号：MX164336B
公开(公告)日：1992-08-04
申请号：MX246086
申请日：1986-05-12
Applicant: TANDEM COMPUTERS INC
Inventor： CHANDRAN SRIKUMAR R , WALKER MARK S
Abstract: The present invention relates to a digital logic circuit and method for synchronizing the leading edges of a skewed true-complement signal pair. The circuit of the present invention is comprised of two similar, interconnected circuit halves, each of which includes three D flip-flop stages. The outputs from the second D flip-flop stages from the two circuit halves are applied to the two inputs of two identical logic gates, such that the signal pair is synchronously transmitted to a pair of output gates through a third D flip-flop stage in each circuit half. The second D flip-flop stages also prevent metastable states from reaching the synchronizer output. Metastable states may result if the input setup time is violated for the first D flip-flop stages. The third D flip-flop stage in each circuit half also eliminates any signal irregularities generated in the logic circuitry from appearing on the synchronizer output lines. The present invention is self-checking in that any single fault in the input signals or in the synchronizer circuit itself will result in the synchronizer output pair not having a true complement relationship.
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公开(公告)号：AU5720386A
公开(公告)日：1986-11-13
申请号：AU5720386
申请日：1986-05-07
Applicant: TANDEM COMPUTERS INC
Inventor： CHANDRAN SRIKUMAR R , WALKER MARK S
Abstract: The present invention relates to a digital logic circuit and method for synchronizing the leading edges of a skewed true-complement signal pair. The circuit of the present invention is comprised of two similar, interconnected circuit halves, each of which includes three D flip-flop stages. The outputs from the second D flip-flop stages from the two circuit halves are applied to the two inputs of two identical logic gates, such that the signal pair is synchronously transmitted to a pair of output gates through a third D flip-flop stage in each circuit half. The second D flip-flop stages also prevent metastable states from reaching the synchronizer output. Metastable states may result if the input setup time is violated for the first D flip-flop stages. The third D flip-flop stage in each circuit half also eliminates any signal irregularities generated in the logic circuitry from appearing on the synchronizer output lines. The present invention is self-checking in that any single fault in the input signals or in the synchronizer circuit itself will result in the synchronizer output pair not having a true complement relationship.
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公开(公告)号：NO861862L
公开(公告)日：1986-11-11
申请号：NO861862
申请日：1986-05-09
Applicant: TANDEM COMPUTERS INC
Inventor： CHANDRAN SRIKUMAR R , WALKER MARK S
Abstract: The present invention relates to a digital logic circuit and method for synchronizing the leading edges of a skewed true-complement signal pair. The circuit of the present invention is comprised of two similar, interconnected circuit halves, each of which includes three D flip-flop stages. The outputs from the second D flip-flop stages from the two circuit halves are applied to the two inputs of two identical logic gates, such that the signal pair is synchronously transmitted to a pair of output gates through a third D flip-flop stage in each circuit half. The second D flip-flop stages also prevent metastable states from reaching the synchronizer output. Metastable states may result if the input setup time is violated for the first D flip-flop stages. The third D flip-flop stage in each circuit half also eliminates any signal irregularities generated in the logic circuitry from appearing on the synchronizer output lines. The present invention is self-checking in that any single fault in the input signals or in the synchronizer circuit itself will result in the synchronizer output pair not having a true complement relationship.
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