公开(公告)号：JPH022236A

公开(公告)日：1990-01-08

申请号：JP30046188

申请日：1988-11-28

Applicant: TANDEM COMPUTERS INC

Inventor： MAATEIN DABURIYUU SANAA

IPC: G06F1/12 ,  H03K5/00 ,  H03K5/135 ,  H04L7/02

Abstract: PURPOSE: To synchronize the rise of an input signal with the transition of a clock signal within one period of a clock signal at maximum by providing the two-step type synchronizing device with a pair of flip flops(FFs) constituted to write an input signal at the time of transition of a periodical pulse string to a positive pole or a negative pole. CONSTITUTION: At the time of transition of a CLK signal to the positive pole, an FF 12 writes an IN signal, and at the time of transition of the CLK signal to the negative pole, an FF 14 writes an IN signal. Output signals from the FFs 12, 14 are inputted to an OR gate 20 and respectively transmitted to the data(D) input terminals of FFs 16, 18. All of three output signals O1 to O3 form the display format of the IN signal synchronized with the transition of the CLK signal. Similar analysis can be applied also to the transition of the IN signal to the negative pole.

公开(公告)号：JPH01280843A

公开(公告)日：1989-11-13

申请号：JP30046388

申请日：1988-11-28

Applicant: TANDEM COMPUTERS INC

Inventor： MAATEIN DABURIYUU SANAA ,  SHIIMA CHIYANDORA

IPC: G06F11/30 ,  G06F11/00 ,  G06F11/26 ,  G06F11/28 ,  G06F13/00

Abstract: PURPOSE: To guarantee the correct operation of a state machine by rewriting a slave state machine by an emulator in response to control signals from a master state machine, checking respective assumed states rewritten by the emulator and generating error signals in the case of an erroneous operation. CONSTITUTION: The slave state machine 40 to be rewritten by the emulator receives signals from a state decoder 34 for assuming the states same as the ones assumed by the state machine of a slave control unit 22. The output of the slave state machine 40 is added to a state sequence checker unit similarly to the output of the master state machine 30. A state sequence checker 42 performs checking by a method for deciding whether or not the respective states assumed by the two state machines 30 and 40 are correct, and when they are not correct, the state sequence checker 42 originates the error signals for indicating a problem. Thus, the correct operation of the state machine is guaranteed.

公开(公告)号：JPH01280838A

公开(公告)日：1989-11-13

申请号：JP30046288

申请日：1988-11-28

Applicant: TANDEM COMPUTERS INC

Inventor： MAATEIN DABURIYUU SANAA

IPC: G06F11/10

Abstract: PURPOSE: To ensure the detection and separation of errors by monitoring the completeness of data made to cross the input boundary of a digital sub system and transmitted through various combination logic provided inside the boundary to the output of the sub system. CONSTITUTION: Three points for checking the completeness of the data, that are a parity checking circuit 30, the parity checking circuit 48 and exclusive OR and AND gates 50 and 52, are provided inside the sub system 10. Then, the check points are provided with three error signals, that are a bus A error, a parity reproduction error and a bus B error, and they successively give the instruction of a part where the error is generated. Thus, the generation of a parity error on the sub system is surely checked and separated.

公开(公告)号：JPH01280842A

公开(公告)日：1989-11-13

申请号：JP30046588

申请日：1988-11-28

Applicant: TANDEM COMPUTERS INC

Inventor： MAATEIN DABURIYUU SANAA

IPC: G06F11/22 ,  G01R31/3185

Abstract: PURPOSE: To eliminate data loss due to clocking delay by making a sub chain for receiving the different type with less delay of scanning clocks appear after a scanning line. CONSTITUTION: The distribution of the sub chains 12, 14, 16, 18 and 20 in the entire scanning line 10 formed when SCAN EN is asserted is decided by the different type of system clocks(SYSCLK) received by the sub chains 12, 14, 16, 18 and 20. The sub chains 12, 14, 16, 18 and 20 receive the scanning line of the different type with the least delay. Thus, the sub chain 20 for receiving the SYSCLK of the different type without the delay is placed at the end of the scanning line. Thus, the data loss due to delay clocks is eliminated.

公开(公告)号：JPH01205237A

公开(公告)日：1989-08-17

申请号：JP30046488

申请日：1988-11-28

Applicant: TANDEM COMPUTERS INC

Inventor： MAATEIN DABURIYUU SANAA

IPC: G06F1/04 ,  G06F11/00 ,  H03K5/00 ,  H04L1/24 ,  H04L7/00

Abstract: PURPOSE: To guarantee the correct operation of a circuit by generating an error signal when two input pulses are received without any interstitial output pulse. CONSTITUTION: A synchronizing circuit 12 is coupled with an event counter 10 and receives an input signal IN and a clock signal CLK on a signal line 14 and generates an output signal OUT on a line 16. Operation is performed by showing the events of the input pulses to the synchronizing circuit 12 and respective displays (representation) generated by the circuit, a comparison is made so as to guarantee the generation of synchronized representations for the respective input events, and if no representation is generated, an error signal is generated so as to indicate a function failure of a device. Consequently, a fault of the synchronizing circuit 12 can be detected.