公开(公告)号：JPH03230222A

公开(公告)日：1991-10-14

申请号：JP32516190

申请日：1990-11-27

Applicant: TANDEM COMPUTERS INC

Inventor： ROBAATO DABURIYUU HOOSUTO ,  MAIZANUA EMU RAAMAN ,  RICHIYAADO HARISU

IPC: G06F9/22 ,  G06F9/26 ,  G06F9/28

Abstract: PURPOSE: To perform 2-cycle RAM access without sacrificing performance by using the first and second banks of a control memory and storing micro- instructions. CONSTITUTION: A calculation system 10 is provided with a macroinstruction processor (IPU) 14 for storing and taking out macroinstructions, this micro- instruction sequencer 22 for generating the micro-instructions corresponding to the macro-instructions stored inside the IPU 14 and a data processor (DPU) 26 for storing and processing data corresponding to instructions from the IPU 14 and the micro-instruction sequencer 22. Then, the micro-instruction sequencer 22 communicates with the IPU 14 and the DPU 26 respectively through an IPU-sequencer bus 30 and a DPU-sequencer bus 36. Also, the IPU 14 communicates with the DPU 26 through an IPU-DPU bus 37. Thus, the DPU 26 starts the execution of the micro-instruction at a rank 1 while a first micro- instruction is executed at the rank 2.