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公开(公告)号：JPH0228860A
公开(公告)日：1990-01-30
申请号：JP8954889
申请日：1989-04-07
Applicant: TANDEM COMPUTERS INC
Inventor： UIN EMU CHIYAN
Abstract: PURPOSE: To highten a data rate while giving access for transferring data to a peripheral device of a low priority order by automatically adjusting the burst length of data transferred between a processor unit and the peripheral device. CONSTITUTION: Plural device controllers 14, 16 and 18 are connected to the processor unit 12 through an I/O bus 20. In the middle of a data transferring cycle, a device controller controlling data transfer monitors the I/O bus with respect to the generation of a request signal from another device controller. At the time of detecting the generation of the request signal and instructing that not less than one other device controllers request a data transfer cycle, a present data transferring cycle interrupts after a prescribed event. The interrupted device controller waits in some period before requesting access to the I/O bus 20 so that another peripheral device may join the data transferring cycle with the processor unit 12.
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公开(公告)号：JPH01188953A
公开(公告)日：1989-07-28
申请号：JP30046088
申请日：1988-11-28
Applicant: TANDEM COMPUTERS INC
Inventor： UIN EMU CHIYAN
Abstract: PURPOSE: To provide a data maintaining device having an excellent fault allowable range capability by providing two control means for error correction code generation and error detection and generating an error correction code by one of these means and detecting an error by the other. CONSTITUTION: When data transmitted from a CPU through a bus 10 is stored in a storage device 14, one of two device control units 40a and 40b generates the code and adds it to this data. At this time, the other device control unit uses the added correction code to detect an error, thereby inspecting the function of the device control unit for code generation. One device control unit may generate the error correction code and detect an error even if the other is faulty.
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公开(公告)号：JPH06242887A
公开(公告)日：1994-09-02
申请号：JP26344692
申请日：1992-10-01
Applicant: TANDEM COMPUTERS INC
Inventor： MAAKU UOOKAA , ARUBAATO ESU RUI , HARARUDO SAMAA , UIN EMU CHIYAN , UIRIAMU TEII FURAA
IPC: G06F11/18 , G06F9/52 , G06F15/173 , G06F3/06 , G06F15/16
Abstract: PURPOSE: To provide a computer system which can secure the optimum matching between the I/O band width of a data storage array system and the I/O performance of a CPU. CONSTITUTION: A plurality of CPU1 are freely and directly connected to a plurality of disk arrays 4 via a switching network. Thus, it is possible to make up such a computer system that can secure the optimum matching between the I/O band width of every array 4 and the I/O performance of every CPU1 by connecting these array and CPU together using the switching network.
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