公开(公告)号：JPH06301528A

公开(公告)日：1994-10-28

申请号：JP3481694

申请日：1994-03-04

Applicant: TANDEM COMPUTERS INC

Inventor： UIRIAMU TEII FURAA

IPC: G06F9/22 ,  G06F9/26 ,  G06F9/28 ,  G06F9/38 ,  G06F11/30

Abstract: PURPOSE: To enable a digital device which becomes a subsystem to achieve a timer function when the condition of a branch microinstruction does not appear. CONSTITUTION: This digital device is provided with an address register 32 which is connected to a storage device 30 so that the register 32 can operate in accordance with instructions successively accessed from the device 30 to test whether or not a condition signal appears within a prescribed period of time and operates in first and second modes and the register 32 performs access to instructions from the device by sequentially generating address signals in the first mode and measures the prescribed period of time in the second mode. The register 32 is provided with an incrementing means 50 which increments a holding value and a means 60 which generates a time-out signal when no condition signal exists within the prescribed period of time.

公开(公告)号：JPH0679270B2

公开(公告)日：1994-10-05

申请号：JP5868287

申请日：1987-03-13

Applicant: TANDEM COMPUTERS INC

Inventor： UIRIAMU TEII FURAA

IPC: G06F9/22 ,  G06F9/26 ,  G06F9/28 ,  G06F9/38 ,  G06F11/30

公开(公告)号：JPS62235839A

公开(公告)日：1987-10-16

申请号：JP7295687

申请日：1987-03-26

Applicant: TANDEM COMPUTERS INC

Inventor： UIRIAMU TEII FURAA

IPC: G06F13/22

公开(公告)号：JPH06242887A

公开(公告)日：1994-09-02

申请号：JP26344692

申请日：1992-10-01

Applicant: TANDEM COMPUTERS INC

Inventor： MAAKU UOOKAA ,  ARUBAATO ESU RUI ,  HARARUDO SAMAA ,  UIN EMU CHIYAN ,  UIRIAMU TEII FURAA

IPC: G06F11/18 ,  G06F9/52 ,  G06F15/173 ,  G06F3/06 ,  G06F15/16

Abstract: PURPOSE: To provide a computer system which can secure the optimum matching between the I/O band width of a data storage array system and the I/O performance of a CPU. CONSTITUTION: A plurality of CPU1 are freely and directly connected to a plurality of disk arrays 4 via a switching network. Thus, it is possible to make up such a computer system that can secure the optimum matching between the I/O band width of every array 4 and the I/O performance of every CPU1 by connecting these array and CPU together using the switching network.

公开(公告)号：JPH06208476A

公开(公告)日：1994-07-26

申请号：JP857893

申请日：1993-01-21

Applicant: TANDEM COMPUTERS INC

Inventor： UIRIAMU TEII FURAA

IPC: G06F3/06 ,  G06F11/10 ,  G06F12/08 ,  G06F12/16

Abstract: PURPOSE: To improve the characteristics of a storing subsystem by suppressing the number of performing times of access to a required storage unit so as to improve the I/O characteristic of a redundant storage array system. CONSTITUTION: A redundant array parity caching system is provided with an RRR-parity cache 5 and a controller 3 which discriminates RRR-parity blocks and caches the cache 5. The RRR-parity block is equal to the exclusive OR of an old data block and an old parity block read out from a line having the same redundancy as that the old data block has. When the RRR-parity block is cached, therefore, the action of a write-intensive storage unit can be reduced by three I/O accessing times in maximum.

公开(公告)号：JPS62224826A

公开(公告)日：1987-10-02

申请号：JP5868287

申请日：1987-03-13

Applicant: TANDEM COMPUTERS INC

Inventor： UIRIAMU TEII FURAA

IPC: G06F9/22 ,  G06F9/26 ,  G06F9/28 ,  G06F9/38 ,  G06F11/30