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公开(公告)号：DE3750680T2
公开(公告)日：1995-03-09
申请号：DE3750680
申请日：1987-03-13
Applicant: TANDEM COMPUTERS INC
Inventor： LILJA DAVID J , ZACHER RICHARD A , WIERENGA STEVEN W
Abstract: A bus protocol system for interprocessor communications. The protocol system polls the processors in an open loop fashion to determine which processors are ready to send. Upon completion of a simultaneous poll of all processors the system identifies which processors are ready to send by utilizing a send mask generated by the ready processors. The ready processors are sequentially selected as send processors and granted access to the bus for a complete data transfer cycle unless the selected processor indicates it is not ready to send. The system also includes a timing signal system that provides for a high data transfer rate. A send clock signal strobes words onto the bus from a send processor and a receive clock signal loads words from the bus to a receive processor. The send processor generates the receive clock signal by delaying the send clock signal by a fixed delay, DR.
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Patent Agency Ranking
公开(公告)号：DE3752205T2
公开(公告)日：1999-04-22
申请号：DE3752205
申请日：1987-03-13
Applicant: TANDEM COMPUTERS INC
Inventor： LILJA DAVID J DEPT OF ELECTRIC , ZACHER RICHARD A , WIERENGA STEVEN W
Abstract: A bus protocol system for interprocessor communications. The protocol system polls the processors in an open loop fashion to determine which processors are ready to send. Upon completion of a simultaneous poll of all processors the system identifies which processors are ready to send by utilizing a send mask generated by the ready processors. The ready processors are sequentially selected as send processors and granted access to the bus for a complete data transfer cycle unless the selected processor indicates it is not ready to send. The system also includes a timing signal system that provides for a high data transfer rate. A send clock signal strobes words onto the bus from a send processor and a receive clock signal loads words from the bus to a receive processor. The send processor generates the receive clock signal by delaying the send clock signal by a fixed delay, DR.
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公开(公告)号：DE3750680D1
公开(公告)日：1994-12-01
申请号：DE3750680
申请日：1987-03-13
Applicant: TANDEM COMPUTERS INC
Inventor： LILJA DAVID J , ZACHER RICHARD A , WIERENGA STEVEN W
Abstract: A bus protocol system for interprocessor communications. The protocol system polls the processors in an open loop fashion to determine which processors are ready to send. Upon completion of a simultaneous poll of all processors the system identifies which processors are ready to send by utilizing a send mask generated by the ready processors. The ready processors are sequentially selected as send processors and granted access to the bus for a complete data transfer cycle unless the selected processor indicates it is not ready to send. The system also includes a timing signal system that provides for a high data transfer rate. A send clock signal strobes words onto the bus from a send processor and a receive clock signal loads words from the bus to a receive processor. The send processor generates the receive clock signal by delaying the send clock signal by a fixed delay, DR.
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公开(公告)号：DE3752205D1
公开(公告)日：1998-09-03
申请号：DE3752205
申请日：1987-03-13
Applicant: TANDEM COMPUTERS INC
Inventor： LILJA DAVID J DEPT OF ELECTRIC , ZACHER RICHARD A , WIERENGA STEVEN W
Abstract: A bus protocol system for interprocessor communications. The protocol system polls the processors in an open loop fashion to determine which processors are ready to send. Upon completion of a simultaneous poll of all processors the system identifies which processors are ready to send by utilizing a send mask generated by the ready processors. The ready processors are sequentially selected as send processors and granted access to the bus for a complete data transfer cycle unless the selected processor indicates it is not ready to send. The system also includes a timing signal system that provides for a high data transfer rate. A send clock signal strobes words onto the bus from a send processor and a receive clock signal loads words from the bus to a receive processor. The send processor generates the receive clock signal by delaying the send clock signal by a fixed delay, DR.
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公开(公告)号：DE3852420T2
公开(公告)日：1995-06-01
申请号：DE3852420
申请日：1988-04-11
Applicant: TANDEM COMPUTERS INC
Inventor： ZACHER RICHARD A , ZWAGERMAN JAY A , DWAN FRANCIS J
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公开(公告)号：DE3852420D1
公开(公告)日：1995-01-26
申请号：DE3852420
申请日：1988-04-11
Applicant: TANDEM COMPUTERS INC
Inventor： ZACHER RICHARD A , ZWAGERMAN JAY A , DWAN FRANCIS J
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