公开(公告)号：WO1995008856A1

公开(公告)日：1995-03-30

申请号：PCT/US1994008812

申请日：1994-08-05

Applicant: TESSERA, INC.

Inventor： TESSERA, INC. ,  SWEIS, Jason ,  GILLEO, Kenneth, Burton

IPC: H01R43/00

CPC classification number: G06K19/07745 ,  H01L21/54 ,  H01L23/24 ,  H01L2924/0002 ,  Y10T29/49144 ,  H01L2924/00

Abstract: A method for creating an interface between a chip (10) and chip carrier (26) includes spacing the chip (10) a given distance above the chip carrier (26), and then introducing a liquid (50) in the gap (34) between the chip (10) and carrier (26). Preferably, the liquid (50) is an elastomer which is hardened into a resilient layer after its introduction into the gap (34). In another preferred embodiment, the terminals (331-34) on a chip carrier (326) are planarized or otherwise vertically positioned by deforming the terminals (331-34) into set vertical locations with a plate (380), and then hardening a liquid (350) between the chip carrier (326) and chip (310).

Abstract translation: 一种用于在芯片（10）和芯片载体（26）之间创建界面的方法包括将芯片（10）与芯片载体（26）上方给定的距离间隔开，然后将液体（50）引入间隙（34） 在芯片（10）和载体（26）之间。 优选地，液体（50）是在其引入间隙（34）之后被硬化成弹性层的弹性体。 在另一优选实施例中，芯片载体（326）上的端子（331-34）通过使端子（331-34）变形成具有板（380）的设定垂直位置而被平坦化或以其它方式垂直定位，然后使液体 （350）在芯片载体（326）和芯片（310）之间。

公开(公告)号：WO1995003685A1

公开(公告)日：1995-02-02

申请号：PCT/US1994008224

申请日：1994-07-21

Applicant: TESSERA, INC.

Inventor： TESSERA, INC. ,  DISTEFANO, Thomas, H. ,  KHANDROS, Igor, Y. ,  MATHIEW, Gaetan ,  SWEIS, Jason ,  GRANGE, John ,  GRUBE, Gary, W.

IPC: H05K03/32

CPC classification number: H01L21/67138 ,  B23K20/025 ,  B23K20/106 ,  H01L24/80 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01045 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01082

Abstract: A bonding tool (20) for bonding inner leads (58, 60, 62, 64) to semiconductor chips (50) is arranged to capture and align elongated lead sections (58, 60, 62, 64) extending in any one of plural direction, and preferably, in any one of two mutually orthogonal directions (26, 28). Thus, the tool (20) can be applied to align and bond all of the leads (58, 60, 62, 64) to a chip (50) without turning the tool (20) or the chip (50) even where the leads (58, 60, 62, 64) extend in multiple directions.

Abstract translation: 用于将内引线（58,60,62,64）连接到半导体芯片（50）的接合工具（20）被布置成捕获并对准沿多个方向中的任一个延伸的细长引线部分（58,60,62,64） ，优选地，在两个相互正交的方向（26,28）中的任一个中。 因此，工具（20）可以应用于将所有引线（58,60,62,64）对齐并结合到芯片（50），而不转动工具（20）或芯片（50），即使在引线 （58,60,62,64）在多个方向上延伸。

公开(公告)号：WO1995003152A1

公开(公告)日：1995-02-02

申请号：PCT/US1994008234

申请日：1994-07-21

Applicant: TESSERA, INC.

Inventor： TESSERA, INC. ,  GRUBE, Gary, W. ,  MATHIEW, Gaetan ,  SWEIS, Jason ,  GRANGE, John

IPC: B23K31/02

CPC classification number: H01L24/50 ,  B23K20/10 ,  B23K2101/40 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01079 ,  H01L2924/01082

Abstract: In a semiconductor inner lead bonding process, a connection component having leads is disposed on a chip surface so that leads lie above contacts (54). A bond region (62) of each lead is forced downwardly by a tool (60) into engagement with a contact (54) on the chip while a first or proximal end (38) of the lead remains attached to a dielectric support structure. The lead is deformed into an S-shaped configuration by moving the bonding tool (60) horizontally towards the proximal or first end (38) of the lead, thereby forcing the bonding region (62) towards the first end (38) and bending or buckling the lead. Alternatively, the lead is bent downwardly by a tool and the tool may then be disengaged from the lead, shifted away from the proximal end (38) of the lead and again advanced downwardly to secure the lead to the chip contact (54).

Abstract translation: 在半导体内引线接合工艺中，具有引线的连接部件设置在芯片表面上，使得引线位于触点（54）上方。 每个引线的接合区域（62）被工具（60）向下推动成与芯片上的触点（54）接合，同时引线的第一或近端（38）保持附接到电介质支撑结构。 通过将接合工具（60）水平地朝向引线的近端或第一端（38）移动，引线变形为S形构造，从而迫使接合区域（62）朝向第一端（38）并弯曲或 屈服领先。 或者，引线通过工具向下弯曲，然后工具可以从引线脱离，从引线的近端（38）移开，并再次向前推进以将引线固定到芯片接触（54）。

公开(公告)号：EP0674814A1

公开(公告)日：1995-10-04

申请号：EP94924580.0

申请日：1994-08-05

Applicant: TESSERA, INC.

Inventor： SWEIS, Jason ,  GILLEO, Kenneth, Burton

IPC: H01L23 ,  G06K19 ,  H01L21

CPC classification number: G06K19/07745 ,  H01L21/54 ,  H01L23/24 ,  H01L2924/0002 ,  Y10T29/49144 ,  H01L2924/00

Abstract: A method for creating an interface between a chip (10) and chip carrier (26) includes spacing the chip (10) a given distance above the chip carrier (26), and then introducing a liquid (50) in the gap (34) between the chip (10) and carrier (26). Preferably, the liquid (50) is an elastomer which is hardened into a resilient layer after its introduction into the gap (34). In another preferred embodiment, the terminals (331-34) on a chip carrier (326) are planarized or otherwise vertically positioned by deforming the terminals (331-34) into set vertical locations with a plate (380), and then hardening a liquid (350) between the chip carrier (326) and chip (310).