公开(公告)号：WO1996002068A1

公开(公告)日：1996-01-25

申请号：PCT/US1995008182

申请日：1995-06-29

Applicant: TESSERA, INC.

Inventor： TESSERA, INC. ,  DISTEFANO, Thomas, H. ,  SMITH, John, W.

IPC: H01L21/60

CPC classification number: H01L23/4985 ,  H01L21/4839 ,  H01L23/22 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/642 ,  H01L24/72 ,  H01L2224/16 ,  H01L2224/45124 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01066 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/3025 ,  H01L2924/351 ,  H05K1/118 ,  H05K3/361 ,  H05K3/4084 ,  H05K2201/0133 ,  H05K2201/0394 ,  H05K2201/0397 ,  H05K2201/09081 ,  H05K2201/091 ,  H05K2203/063 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49158 ,  H01L2924/00 ,  H01L2224/48

Abstract: A microelectronic connection component includes a dielectric sheet (34) having an area array of elongated, strip-like leads (60). Each lead has a terminal end (66) fastened to the sheet and a tip end (68) detachable from the sheet. Each lead extends horizontally parallel to the sheet, from its terminal end to its tip end. The tip ends are attached to a second element, such as another dielectric sheet or a semiconductor wafer (86). The first and second elements are then moved relative to one another to advance the tip end of each lead vertically away from the dielectric sheet and deform the leads into a bent, vertically extensive configuration. The preferred structures provide semiconductor chip assemblies with a planar area array of contacts on the chip, an array of terminals on the sheet positioned so that each terminal is substantially over the corresponding contact, and an array of metal S-shaped ribbons connected between the terminals and contacts. A compliant dielectric material may be provided between the sheet and chip, substantially surrounding the S-shaped ribbons.

Abstract translation: 微电子连接部件包括具有细长带状引线（60）的区域阵列的电介质片（34）。 每个引线具有紧固到片材的末端（66）和可从片材上拆卸的尖端（68）。 每个引线从其终端到其尖端水平平行地延伸。 尖端附接到第二元件，例如另一个电介质片或半导体晶片（86）。 然后，第一和第二元件相对于彼此移动，以使每个引线的尖端垂直远离电介质片，并将引线变形成弯曲的垂直广泛配置。 优选的结构提供半导体芯片组件，其具有在芯片上的平面区域阵列的触点，片材上的端子阵列被定位成使得每个端子基本上在相应的触点上方，以及连接在端子之间的金属S形带阵列 和联系人。 柔性电介质材料可以设置在片和芯片之间，基本上围绕S形带。

公开(公告)号：WO1994023451A1

公开(公告)日：1994-10-13

申请号：PCT/US1994003346

申请日：1994-03-28

Applicant: TESSERA, INC.

Inventor： TESSERA, INC. ,  GRUBE, Gary ,  KHANDROS, Igor ,  MATHIEU, Gaetan

IPC: H01L23/42

CPC classification number: H01L24/72 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/351 ,  Y10T29/49004 ,  Y10T29/4913 ,  H01L2924/00

Abstract: A semiconductor chip assembly includes a chip (20), terminals (34) permanently electrically connected to the chip by flexible leads (36) and a resilient element (48) or elements for biasing the terminals away from the chip. The chip is permanently engaged with a substrate (52) having contact pads (58) so that the terminals are disposed between the chip and the substrate and the terminals engage the contact pads under the influence of the force applied by the resilient element. The terminals typically are provided on a flexible sheet-like dielectric interposer (28) and the resilient element is disposed between the interposer and the chip. The assembly of the chip and the terminals can be tested prior to engagement with the substrate. Engagement of this assembly with the substrate does not involve soldering or other complex bonding processes. The assembly may occupy an area only slightly larger than the area of the chip itself.

Abstract translation: 半导体芯片组件包括芯片（20），通过柔性引线（36）和弹性元件（48）永久地电连接到芯片的端子（34）或用于将端子偏压离开芯片的元件。 芯片与具有接触焊盘（58）的基板（52）永久地接合，使得端子设置在芯片和基板之间，并且端子在由弹性元件施加的力的影响下接合接触焊盘。 端子通常设置在柔性片状电介质插入件（28）上，并且弹性元件设置在插入件和芯片之间。 可以在与基板接合之前测试芯片和端子的组件。 该组件与衬底的接合不涉及焊接或其它复杂的结合工艺。 组件可以占据仅稍大于芯片本身的面积的区域。

公开(公告)号：WO1996034744A1

公开(公告)日：1996-11-07

申请号：PCT/US1996006228

申请日：1996-05-03

Applicant: TESSERA, INC.

Inventor： TESSERA, INC. ,  FJELSTAD, Joseph ,  SMITH, John, W.

IPC: B32B31/12

CPC classification number: H05K3/4092 ,  H01L23/4985 ,  H01L24/80 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  Y10T29/49121 ,  Y10T29/49222 ,  Y10T156/1052 ,  H01L2924/00

Abstract: A substantially continuous layer of a first metal (137) such as copper is provided with strips of a second metal (147) such as gold by selective electroplating of the second metal, or by applying separately formed strips such as lengths of wire. A dielectric support layer (132) is provided in contact with the first metal layer, and the first metal layer is etched to leave strips of the first metal continuous with the strips of the second metal, thereby providing composite leads with the first and second metal strips connected in series. The process provides simple and economical methods of making microelectronic connection components with leads having a flexible, fatigue resistant lead portion formed from a precious metal. The leads may incorporate sections of round cross-sectional shape to facilitate engagement by a bonding tool during use of the component.

Abstract translation: 第一金属（137）如铜的基本上连续的层通过第二金属的选择性电镀或通过施加单独形成的条（例如一段电线）而设置有诸如金的第二金属（147）的条。 提供与第一金属层接触的电介质支撑层（132），并且蚀刻第一金属层以留下与第二金属的条带连续的第一金属的条带，由此提供具有第一和第二金属的复合引线 条带串联连接。 该方法提供了简单和经济的方法来制造具有由贵金属形成的柔性耐疲劳导线部分的引线的微电子连接部件。 引线可以包括圆形横截面形状的部分，以便于在部件的使用期间通过焊接工具的接合。

公开(公告)号：WO1996009746A1

公开(公告)日：1996-03-28

申请号：PCT/US1995011933

申请日：1995-09-20

Applicant: TESSERA, INC.

Inventor： TESSERA, INC. ,  KOVAC, Zlata ,  MITCHELL, Craig ,  DISTEFANO, Thomas

IPC: H05K01/02

CPC classification number: H01L24/81 ,  H01L21/56 ,  H01L21/563 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/4985 ,  H01L24/72 ,  H01L24/75 ,  H01L2224/16 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/75 ,  H01L2224/75301 ,  H01L2224/81801 ,  H01L2224/83136 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/16152 ,  H01L2924/19041 ,  H01L2924/19043 ,  H05K1/118 ,  H05K3/361 ,  H05K3/4084 ,  H05K2201/0133 ,  H05K2201/0394 ,  H05K2201/0397 ,  H05K2201/09081 ,  H05K2201/091 ,  H05K2203/063 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49174 ,  H01L2924/00014

Abstract: A method and an apparatus for providing a planar and compliant interface between a semiconductor chip (120) and its supporting substrate to accommodate for the thermal coefficient of expansion mismatch therebetween. The compliant interface is comprised of a plurality of compliant pads (110) defining channels (117) between adjacent pads. The pads are typically compressed between a flexible film chip carrier (100) and the chip. A compliant filler (170) is further disposed within the channels to form a uniform encapsulation layer having a controlled thickness.

Abstract translation: 一种用于在半导体芯片（120）和其支撑衬底之间提供平面和柔性界面的方法和装置，以适应其之间的热膨胀系数不匹配。 兼容接口由在相邻焊盘之间限定通道（117）的多个柔性焊盘（110）组成。 垫通常在柔性膜芯片载体（100）和芯片之间被压缩。 进一步在通道内设置顺应填料（170）以形成具有受控厚度的均匀包封层。

公开(公告)号：WO1995003685A1

公开(公告)日：1995-02-02

申请号：PCT/US1994008224

申请日：1994-07-21

Applicant: TESSERA, INC.

Inventor： TESSERA, INC. ,  DISTEFANO, Thomas, H. ,  KHANDROS, Igor, Y. ,  MATHIEW, Gaetan ,  SWEIS, Jason ,  GRANGE, John ,  GRUBE, Gary, W.

IPC: H05K03/32

CPC classification number: H01L21/67138 ,  B23K20/025 ,  B23K20/106 ,  H01L24/80 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01045 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01082

Abstract: A bonding tool (20) for bonding inner leads (58, 60, 62, 64) to semiconductor chips (50) is arranged to capture and align elongated lead sections (58, 60, 62, 64) extending in any one of plural direction, and preferably, in any one of two mutually orthogonal directions (26, 28). Thus, the tool (20) can be applied to align and bond all of the leads (58, 60, 62, 64) to a chip (50) without turning the tool (20) or the chip (50) even where the leads (58, 60, 62, 64) extend in multiple directions.

Abstract translation: 用于将内引线（58,60,62,64）连接到半导体芯片（50）的接合工具（20）被布置成捕获并对准沿多个方向中的任一个延伸的细长引线部分（58,60,62,64） ，优选地，在两个相互正交的方向（26,28）中的任一个中。 因此，工具（20）可以应用于将所有引线（58,60,62,64）对齐并结合到芯片（50），而不转动工具（20）或芯片（50），即使在引线 （58,60,62,64）在多个方向上延伸。

公开(公告)号：WO1997039482A1

公开(公告)日：1997-10-23

申请号：PCT/US1997006498

申请日：1997-04-17

Applicant: TESSERA, INC.

Inventor： TESSERA, INC. ,  FJELSTAD, Joseph

IPC: H01L21/56

CPC classification number: H01L21/568 ,  H01L21/4832 ,  H01L21/56 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/3128 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L25/18 ,  H01L2221/68377 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48472 ,  H01L2224/48475 ,  H01L2224/49171 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/85001 ,  H01L2224/85051 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10162 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/19043 ,  H01L2924/19107 ,  H01L2924/3011 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099

Abstract: A method of manufacturing a semiconductor chip package. A sacrificial layer (100) is used as a base to selectively form an array of conductive pads (110) such that a central region (114) is defined by the pads. A back surface (122) of a semiconductor chip is attached to the sacrificial layer within the central region between the pads so that the contact bearing surface (121) of the chip faces away from the sacrificial layer. The chip contacts are then electrically connected to the respective pads, typically by wire bonding wires (130) therebetween. A liquid encapsulant (140) is then deposited. The encapsulant is cured and the sacrificial layer is either completely removed or is selectively removed to expose a surface of the pads for electrical attachment to a PWB and the back surface of the chip for creating a direct thermal path from the chip to the PWB.

Abstract translation: 一种制造半导体芯片封装的方法。 牺牲层（100）用作基底以选择性地形成阵列的导电焊盘（110），使得中心区域（114）由焊盘限定。 将半导体芯片的背面（122）附接到垫之间的中心区域内的牺牲层，使得芯片的接触支承面（121）背离牺牲层。 然后，芯片触点通常通过其间的引线接合线（130）电连接到相应的焊盘。 然后沉积液体密封剂（140）。 密封剂被固化并且牺牲层被完全去除或被选择性地去除以暴露焊盘的表面以电连接到PWB和芯片的后表面，以形成从芯片到PWB的直接热路径。

公开(公告)号：WO1995003152A1

公开(公告)日：1995-02-02

申请号：PCT/US1994008234

申请日：1994-07-21

Applicant: TESSERA, INC.

Inventor： TESSERA, INC. ,  GRUBE, Gary, W. ,  MATHIEW, Gaetan ,  SWEIS, Jason ,  GRANGE, John

IPC: B23K31/02

CPC classification number: H01L24/50 ,  B23K20/10 ,  B23K2101/40 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01079 ,  H01L2924/01082

Abstract: In a semiconductor inner lead bonding process, a connection component having leads is disposed on a chip surface so that leads lie above contacts (54). A bond region (62) of each lead is forced downwardly by a tool (60) into engagement with a contact (54) on the chip while a first or proximal end (38) of the lead remains attached to a dielectric support structure. The lead is deformed into an S-shaped configuration by moving the bonding tool (60) horizontally towards the proximal or first end (38) of the lead, thereby forcing the bonding region (62) towards the first end (38) and bending or buckling the lead. Alternatively, the lead is bent downwardly by a tool and the tool may then be disengaged from the lead, shifted away from the proximal end (38) of the lead and again advanced downwardly to secure the lead to the chip contact (54).

Abstract translation: 在半导体内引线接合工艺中，具有引线的连接部件设置在芯片表面上，使得引线位于触点（54）上方。 每个引线的接合区域（62）被工具（60）向下推动成与芯片上的触点（54）接合，同时引线的第一或近端（38）保持附接到电介质支撑结构。 通过将接合工具（60）水平地朝向引线的近端或第一端（38）移动，引线变形为S形构造，从而迫使接合区域（62）朝向第一端（38）并弯曲或 屈服领先。 或者，引线通过工具向下弯曲，然后工具可以从引线脱离，从引线的近端（38）移开，并再次向前推进以将引线固定到芯片接触（54）。

公开(公告)号：WO1994003036A1

公开(公告)日：1994-02-03

申请号：PCT/US1993006930

申请日：1993-07-23

Applicant: TESSERA, INC. ,  DISTEFANO, Thomas, H. ,  GRUBE, Gary, W. ,  KHANDROS, Igor, Y. ,  MATHIEW, Gaetan ,  SWEIS, Jason ,  UNION, Laurie ,  GIBSON, David

Inventor： TESSERA, INC.

IPC: H05K03/36

CPC classification number: H01L23/49572 ,  H01L23/3107 ,  H01L23/49838 ,  H01L23/4985 ,  H01L23/49861 ,  H01L24/01 ,  H01L2924/01082 ,  H01L2924/12042 ,  H05K3/361 ,  H05K3/4084 ,  Y10T29/49121 ,  Y10T29/4913 ,  Y10T29/49135 ,  Y10T29/49218 ,  Y10T29/49222 ,  H01L2924/00

Abstract: A connection component for electrically connecting a semiconductor chip to support substrate incorporates a preferably dielectric supporting structure (70) defining gaps (40). Leads extend across these gaps so that the leads are supported on both sides of the gap (66, 70). The leads therefore can be positioned approximately in registration to contacts on the chip by aligning the connection component with the chip. Each lead is arranged so that one end can be displaced relative to the supporting structure when a downward force is applied to the lead. This allows the leads to be connected to the contacts on the chip by engaging each lead with a tool and forcing the lead downwardly against the contact. Preferably, each lead incorporates a frangible section (72) adjacent one side of the gap and the frangible section is broken when the lead is engaged with the contact. Final alignment of the leads with the contacts on the chip is provided by the bonding tool which has features adapted to control the position of the lead.

Abstract translation: 用于将半导体芯片电连接到支撑衬底的连接部件包含限定间隙（40）的优选电介质支撑结构（70）。 引线延伸穿过这些间隙，使得引线被支撑在间隙（66,70）的两侧。 因此，引线可以通过将连接部件与芯片对准而大致对准芯片上的触点。 每个引线被布置成使得当向引线施加向下的力时，一端可相对于支撑结构移位。 这允许引线通过使每个引线与工具接合并将引线向下抵靠接触件而连接到芯片上的触点。 优选地，每个引线包括与间隙的一侧相邻的易碎部分（72），并且当引线与触点接合时，易碎部分断裂。 引线与芯片上的触点的最终对准由具有适于控制引线位置的特征的焊接工具提供。

公开(公告)号：WO1998026476A1

公开(公告)日：1998-06-18

申请号：PCT/US1997023948

申请日：1997-12-12

Applicant: TESSERA, INC.

Inventor： TESSERA, INC. ,  DISTEFANO, Thomas, H. ,  FJELSTAD, Joseph

IPC: H01R23/68

CPC classification number: H05K3/462 ,  H01L23/49827 ,  H01L23/5385 ,  H01L2924/0002 ,  H01R12/523 ,  H05K1/116 ,  H05K3/4623 ,  H05K2201/0195 ,  H05K2201/0382 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/10378 ,  H01L2924/00

Abstract: An interposer (50) for interconnection between microelectronic circuit panels (80, 92) has contacts (70, 90) at its surfaces (63, 64). Each contact extends from a central conductor (72), and has a peripheral portion adapted to contract radially inwardly toward the central conductor (72) in response to a force applied by a contact pad (81, 95) defining a central hole (83) on the engaged circuit panel. Thus, when the circuit panels are compressed with the interposers, the contacts (70, 90) contract radially inwardly and wipe across the pads (81, 95). The wiping action facilitates bonding of the contacts to the pads, as by friction welding, or by a conductive bonding material carried on the contacts themselves.

Abstract translation: 用于微电子电路板（80,92）之间的互连的插入器（50）在其表面（63,64）处具有触点（70,90）。 每个接触件从中心导体（72）延伸，并且响应由限定中心孔（83）的接触垫（81,95）施加的力，具有适于径向向内朝向中心导体（72）收缩的周边部分， 在接合的电路板上。 因此，当电路板被内插件压缩时，触头（70,90）径向向内收缩并擦拭穿过焊盘（81,95）。 擦拭动作有助于通过摩擦焊接将接触件接合到焊盘，或者通过接触件本身承载的导电接合材料。

公开(公告)号：WO1997044859A1

公开(公告)日：1997-11-27

申请号：PCT/US1997008783

申请日：1997-05-22

Applicant: TESSERA, INC.

Inventor： TESSERA, INC. ,  FJELSTAD, Joseph ,  DISTEFANO, Thomas, H. ,  KARAVAKIS, Konstantine ,  FARACI, Anthony, B. ,  NGUYEN, Tan

IPC: H01R09/09

CPC classification number: H01L23/32 ,  H01L23/49827 ,  H01L2224/13111 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/45144 ,  H01L2224/73251 ,  H01L2224/81191 ,  H01L2224/81385 ,  H01L2224/81901 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/351 ,  H01R12/52 ,  H05K3/326 ,  H05K3/3436 ,  H05K3/4092 ,  H05K7/1061 ,  H05K2201/0397 ,  H05K2201/049 ,  H05K2201/10257 ,  H05K2201/10378 ,  H05K2203/041 ,  Y02P70/613 ,  Y10T29/49149 ,  H01L2924/00 ,  H01L2224/16 ,  H01L2224/72

Abstract: A connector (10) for microelectronic elements includes a sheetlike body (24) having a plurality of active contacts (22) arranged in a regular grid pattern. The active contacts (22) may include several metallic projections (28) extending inwardly around a hole (27) in the sheetlike element (24), on a first major surface (32). A support structure such as a grid array of noncollapsing structural posts (23) is on a second major surface (33), and each of the posts (23) is electrically connected to one of the active contacts (22). The grid array of the posts (23) and the grid array of active contacts (22) are offset from one another so that an active contact (22) is surrounded by several posts (23). The posts (23) support the sheetlike element (24) spaced away from a substrate (41) to which the posts (23) are attached. A microelectronic element (45) having bump leads (46) thereon may be engaged by contacting the bump leads (46) with the active contacts (22), and deflecting the sheetlike element (24) between the bump leads (46) on one side and the posts (23) on the other side.

Abstract translation: 用于微电子元件的连接器（10）包括具有以规则网格图案布置的多个有源触点（22）的片状体（24）。 活动触头（22）可以包括在第一主表面（32）上在片状元件（24）内围绕孔（27）向内延伸的几个金属突起（28）。 诸如非隔离结构柱（23）的网格阵列之类的支撑结构位于第二主表面（33）上，并且每个柱（23）电连接到一个有源触点（22）。 柱（23）的格栅阵列和活动触点（22）的网格阵列彼此偏移，使得活动触点（22）被多个柱（23）包围。 支柱（23）支撑与柱（23）连接的基板（41）间隔开的片状元件（24）。 在其上具有凸起引线（46）的微电子元件（45）可以通过使凸块引线（46）与有源触头（22）接触而接合，并且使片状元件（24）在一侧的凸块引线（46）之间偏转 和另一侧的柱（23）。