Abstract:
PROBLEM TO BE SOLVED: To provide a method for manufacturing a folding package which can be inexpensively mass-produced. SOLUTION: A slender strip of a sheet-like base material to which a microminiaturize electronic element like a semiconductor chip is mounted is advanced in the downstream direction through one or more folding stations. A series of parts of the base material is folded so as to form a strip provided with a plurality of the folding packages. The folding packages have mutually oppositely arranged upper side/bottom side extensions and fold areas. One or more microminiature electronic elements are mounted to one or more extensions. The strip including a plurality of the folding packages is wound around a reel or handled by a method other than winding, stored, and fed to a succeeding manufacturing process. It is possible to separate individual folding packages from the strip in the manufacturing process. COPYRIGHT: (C)2006,JPO&NCIPI
Abstract:
A microelectronic unit 400 can include a semiconductor element 401 having a front surface, a microelectronic semiconductor device adjacent to the front surface, contacts 403 at the front surface and a rear surface remote from the front surface. The semiconductor element 401 can have through holes 410 extending from the rear surface through the semiconductor element 401 and through the contacts 403. A dielectric layer 411 can line the through holes 410. A conductive layer 412 may overlie the dielectric layer 411 within the through holes 410. The conductive layer 412 can conductively interconnect the contacts 403 with unit contacts.
Abstract:
A covered chip (10 ) having an optical element (14) integrated in the cover (12) is provided which includes a chip (11) having a front surface (18), an optically active circuit area (16), and bond pads (20) disposed at the front surface. The chip is covered by an at least partially optically translucent or transparent unitary cover (12) that is mounted to the front surface of the chip, and has at least one optical element (14) integrated in the unitary cover. The cover (12) is aligned with the optically active circuit area (16) and vertically spaced from the optically active circuit area.
Abstract:
A microelectronic element such as an imaging semiconductor chip (72) is packaged by bonding a lid wafer (20') having recesses (32) open to its bottom surface to a device wafer (50) including a plurality of the microelectronic elements or chips, so that the recesses overlie active regions such as imaging regions (58) of the device wafer. Where the devices include microlenses (60) associated with an imaging region of each chip, the microlenses may be received in the recesses. Land regions (24') of the lid wafer may be disposed very close to the top surface (52) of the device wafer, as for example, abutting the top surface of the device wafer or separated from such top surface only by an extremely thin coating of a bonding material such as an adhesive or solder. The bonded lid wafer and device wafer may be severed to form individual units (70) . The top surface (22) of the lid wafer may be precisely parallel with the top surface of the device wafer.
Abstract:
A microelectronic package includes a mounting structure (136), a microelectronic element associated with the mounting structure, and a plurality of conductive posts (146) physically connected to the mounting structure and electrically connected to the microelectronic element. The conductive posts (146) project from the mounting structure (136) in an upward direction (Z), at least one of the conductive posts being an offset post. Each offset post has a base (154) connected to the mounting structure (136), the base of each offset post defining a centroid (156). Each offset post also defines an upper extremity (178) having a centroid (160), the centroid of the upper extremity being offset from the centroid (156) of the base (154) in a horizontal offset direction transverse to the upward direction (Z). The mounting structure (136) is adapted to permit tilting of each offset post about a horizontal axis so that the upper extremities (178) may wipe across a contact pad of an opposing circuit board.
Abstract:
A microelectronic package may include front and rear covers (46', 60') overlying the front and rear surfaces of a microelectronic element (22') such as an infrared sensor and spaces between the microelectronic element and the covers to provide thermal isolation. A sensing unit including a microelectronic package may include a reflector (76) spaced from the front cover to provide an analyte space, and the microelectronic element may include an emitter (28) and a detector (30) so that radiation directed from the emitter will be reflected by the sensor to the detector, and such radiation will be affected by the properties of the analyte in the analyte space. Such a unit provides a compact, economical chemical sensor. Other packages include elements such as valves (515, 521) for passing fluids into and out of the spaces within the package itself.
Abstract:
A wafer (20) having a front surface and contacts (28) exposed at the front surface is treated by forming electrically conductive risers (30) projecting upwardly from the contacts as, for example, by electroless plating, and then applying a flowable material over the front surface of the device, around the risers, to form a dielectric layer (36) with the risers exposed at a top surface (38) of the dielectric layer facing away from the device. Traces (42). extending over the top surface of the dielectric layer may be formed, and may be connected to at least some of the risers.
Abstract:
A stacked microelectronic assembly is provided which includes first and second stacked microelectronic elements (101, 102). Each of the first and second microelectronic elements can include a conductive layer (610) extending along a face (608) of such microelectronic element. At least one of the first and second microelectronic elements can include a recess (618) extending from the rear surface towards the front surface, and a conductive via (605) extending from the recess through the bond pad (603) and electrically connected to the bond pad, with a conductive layer (610) connected to the via and extending along a rear face (608) of the microelectronic element (101, 102) towards an edge (620) of the microelectronic element. A plurality of leads (224) can extend from the conductive layers (610) of the first and second microelectronic elements and a plurality of terminals (616) of the assembly can be electrically connected with the leads.
Abstract:
A stacked microelectronic unit (80) is provided which has a top surface (34) and a bottom surface remote from the top surface and a plurality of vertically stacked microelectronic elements (12, 12A) therein, including at least one microelectronic element (12A) having a front face (14A) adjacent to the top surface and a rear face (16A) oriented towards the bottom surface. Each of the microelectronic elements (12, 12A) has traces (24, 24A) extending from contacts (22, 22A) at the front face beyond edges of the microelectronic element. A dielectric layer (116) contacts edges of the microelectronic elements and underlies the rear face of the at least one microelectronic element. Leads are connected to the traces (24, 24A) extending along the dielectric layer (116). Unit contacts (74), exposed at the top surface, are connected to the leads (66).
Abstract:
Methods are provided for fabricating packaged chips (2901) having protective layers, e.g., lids (2912) or other overlying layers (2903) having transparent, partially transparent, or opaque characteristics or a combination of such characteristics. Methods are provided for fabricating the packaged chips. Lidded chip structures (2901) and assemblies (3031) including lidded chips are also provided.