Method for manufacturing ultra-small electronic folding package
    1.
    发明专利
    Method for manufacturing ultra-small electronic folding package 审中-公开
    制造超小型电子折叠包装的方法

    公开(公告)号:JP2005303307A

    公开(公告)日:2005-10-27

    申请号:JP2005113498

    申请日:2005-04-11

    Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing a folding package which can be inexpensively mass-produced. SOLUTION: A slender strip of a sheet-like base material to which a microminiaturize electronic element like a semiconductor chip is mounted is advanced in the downstream direction through one or more folding stations. A series of parts of the base material is folded so as to form a strip provided with a plurality of the folding packages. The folding packages have mutually oppositely arranged upper side/bottom side extensions and fold areas. One or more microminiature electronic elements are mounted to one or more extensions. The strip including a plurality of the folding packages is wound around a reel or handled by a method other than winding, stored, and fed to a succeeding manufacturing process. It is possible to separate individual folding packages from the strip in the manufacturing process. COPYRIGHT: (C)2006,JPO&NCIPI

    Abstract translation: 要解决的问题:提供一种可廉价地批量生产折叠包装的方法。 解决方案:安装有诸如半导体芯片的电子元件微电子元件的片状基材的细长条通过一个或多个折叠台在下游方向前进。 折叠基材的一系列部分以形成设置有多个折叠包装的条带。 折叠包装具有相互相对布置的上侧/底侧延伸部和折叠区域。 一个或多个微型电子元件安装到一个或多个延伸部。 包括多个折叠包装的条被卷绕在卷轴上或通过除卷绕,存储和馈送到后续制造过程之外的方法处理。 在制造过程中可以将单独的折叠包装与条带分开。 版权所有(C)2006,JPO&NCIPI

    LOW PROFILE IMAGE SENSOR PACKAGE
    4.
    发明申请
    LOW PROFILE IMAGE SENSOR PACKAGE 审中-公开
    低剖面图像传感器包装

    公开(公告)号:WO2007059193A2

    公开(公告)日:2007-05-24

    申请号:PCT/US2006044301

    申请日:2006-11-14

    Abstract: A microelectronic element such as an imaging semiconductor chip (72) is packaged by bonding a lid wafer (20') having recesses (32) open to its bottom surface to a device wafer (50) including a plurality of the microelectronic elements or chips, so that the recesses overlie active regions such as imaging regions (58) of the device wafer. Where the devices include microlenses (60) associated with an imaging region of each chip, the microlenses may be received in the recesses. Land regions (24') of the lid wafer may be disposed very close to the top surface (52) of the device wafer, as for example, abutting the top surface of the device wafer or separated from such top surface only by an extremely thin coating of a bonding material such as an adhesive or solder. The bonded lid wafer and device wafer may be severed to form individual units (70) . The top surface (22) of the lid wafer may be precisely parallel with the top surface of the device wafer.

    Abstract translation: 诸如成像半导体芯片(72)的微电子元件通过将具有其底表面开口的凹口(32)的盖晶片(20')结合到包括多个微电子元件或芯片的器件晶片(50)而被封装, 使得凹槽覆盖诸如器件晶片的成像区域(58)的有源区域。 在装置包括与每个芯片的成像区域相关联的微透镜(60)的情况下,微透镜可以被容纳在凹部中。 盖晶片的区域(24')可以非常靠近器件晶片的顶表面(52)设置,例如,邻接器件晶片的顶表面或与顶表面分离,仅极薄 粘合材料如粘合剂或焊料的涂覆。 接合的盖子晶片和器件晶片可以被切断以形成单独的单元(70)。 盖晶片的顶表面(22)可以精确地平行于器件晶片的顶表面。

    MICRO PIN GRID ARRAY WITH WIPING ACTION
    5.
    发明申请
    MICRO PIN GRID ARRAY WITH WIPING ACTION 审中-公开
    微型网格阵列与WIPING动作

    公开(公告)号:WO2005065424A3

    公开(公告)日:2006-07-20

    申请号:PCT/US2004044088

    申请日:2004-12-21

    Abstract: A microelectronic package includes a mounting structure (136), a microelectronic element associated with the mounting structure, and a plurality of conductive posts (146) physically connected to the mounting structure and electrically connected to the microelectronic element. The conductive posts (146) project from the mounting structure (136) in an upward direction (Z), at least one of the conductive posts being an offset post. Each offset post has a base (154) connected to the mounting structure (136), the base of each offset post defining a centroid (156). Each offset post also defines an upper extremity (178) having a centroid (160), the centroid of the upper extremity being offset from the centroid (156) of the base (154) in a horizontal offset direction transverse to the upward direction (Z). The mounting structure (136) is adapted to permit tilting of each offset post about a horizontal axis so that the upper extremities (178) may wipe across a contact pad of an opposing circuit board.

    Abstract translation: 微电子封装包括安装结构(136),与安装结构相关联的微电子元件以及物理连接到安装结构并电连接到微电子元件的多个导电柱(146)。 导电柱(146)从安装结构(136)沿向上的方向(Z)突出,至少一个导电柱是偏移柱。 每个偏移柱具有连接到安装结构(136)的基部(154),每个偏移柱的基部限定重心(156)。 每个偏移柱还限定具有质心(160)的上端(178),上端的质心在垂直于向上方向(Z)的水平偏移方向上偏离基座(154)的重心(156) )。 安装结构(136)适于允许每个偏移柱绕水平轴线倾斜,使得上端(178)可以擦拭相对电路板的接触垫。

    WAFER LEVEL MICROELECTRONIC PACKAGING WITH DOUBLE ISOLATION
    6.
    发明申请
    WAFER LEVEL MICROELECTRONIC PACKAGING WITH DOUBLE ISOLATION 审中-公开
    具有双重隔离的水平微电子封装

    公开(公告)号:WO2006044219A2

    公开(公告)日:2006-04-27

    申请号:PCT/US2005035962

    申请日:2005-10-06

    Abstract: A microelectronic package may include front and rear covers (46', 60') overlying the front and rear surfaces of a microelectronic element (22') such as an infrared sensor and spaces between the microelectronic element and the covers to provide thermal isolation. A sensing unit including a microelectronic package may include a reflector (76) spaced from the front cover to provide an analyte space, and the microelectronic element may include an emitter (28) and a detector (30) so that radiation directed from the emitter will be reflected by the sensor to the detector, and such radiation will be affected by the properties of the analyte in the analyte space. Such a unit provides a compact, economical chemical sensor. Other packages include elements such as valves (515, 521) for passing fluids into and out of the spaces within the package itself.

    Abstract translation: 微电子封装可以包括覆盖诸如红外传感器的微电子元件(22')的前表面和后表面的前盖和后盖(46',60'),以及微电子元件和盖之间的空间以提供热隔离。 包括微电子封装的感测单元可以包括与前盖间隔开以提供分析物空间的反射器(76),并且微电子元件可以包括发射器(28)和检测器(30),使得从发射器引导的辐射将 被传感器反射到检测器,并且这种辐射将受分析物空间中分析物的性质的影响。 这种单元提供了紧凑,经济的化学传感器。 其他包装包括诸如用于将流体进入和流出包装内的空间的阀(515,521)的元件。

    STACKED MICROELECTRONIC ASSEMBLY WITH MICROELECTRONIC ELEMENTS HAVING VIAS EXTENDING THROUGH BOND PADS
    8.
    发明申请
    STACKED MICROELECTRONIC ASSEMBLY WITH MICROELECTRONIC ELEMENTS HAVING VIAS EXTENDING THROUGH BOND PADS 审中-公开
    具有通过粘结垫延伸的VIAS的微电子元件的堆叠微电子组件

    公开(公告)号:WO2010104610A8

    公开(公告)日:2011-11-17

    申请号:PCT/US2010000777

    申请日:2010-03-12

    Abstract: A stacked microelectronic assembly is provided which includes first and second stacked microelectronic elements (101, 102). Each of the first and second microelectronic elements can include a conductive layer (610) extending along a face (608) of such microelectronic element. At least one of the first and second microelectronic elements can include a recess (618) extending from the rear surface towards the front surface, and a conductive via (605) extending from the recess through the bond pad (603) and electrically connected to the bond pad, with a conductive layer (610) connected to the via and extending along a rear face (608) of the microelectronic element (101, 102) towards an edge (620) of the microelectronic element. A plurality of leads (224) can extend from the conductive layers (610) of the first and second microelectronic elements and a plurality of terminals (616) of the assembly can be electrically connected with the leads.

    Abstract translation: 提供堆叠的微电子组件,其包括第一和第二堆叠的微电子元件(101,102)。 第一和第二微电子元件中的每一个可以包括沿着这种微电子元件的面(608)延伸的导电层(610)。 第一和第二微电子元件中的至少一个可以包括从后表面朝向前表面延伸的凹槽(618),以及从凹部穿过接合焊盘(603)延伸并电连接到 接合焊盘,其中导电层(610)连接到通孔并且沿着微电子元件(101,102)的后表面(608)朝着微电子元件的边缘(620)延伸。 多个引线(224)可以从第一和第二微电子元件的导电层(610)延伸,并且组件的多个端子(616)可以与引线电连接。

Patent Agency Ranking