Abstract:
unidade de microeletrônica, conjunto microeletrônico, métodos de fabricação de uma unidade de microeletrônica e de fabricação de um conjunto empilhado de unidades microeletrônicas, e, sistema. é divulgada uma unidade de microeletrônica que inclui uma estrutura de suporte com uma superfície frontal, uma superfície traseira remota em relação à superfície frontal, e um rebaixo com uma abertura na superfície frontal e uma superfície interna localizada abaixo da superfície frontal da estrutura de suporte. a unidade de microeletrônica pode incluir um elemento microeletrônico com uma superfície de base adjacente à superfície interna, uma superfície de topo remota em relação à superfície de base e uma pluralidade de contatos na superfície de topo. o elemento microeletrônico pode incluir terminais eletricamente conectados nos contatos do elemento microeletrônico. a unidade de microeletrônico pode incluir uma região dielétrica que contata pelo menos a superfície de topo do elemento microeletrônico. a região dielétrica pdoe ter uma superfície plana localizadacoplanar em relação à superfície frontal da estrutura de suporte, ou acima dela. os terminais podem ficar expostos na superfície da região dielétrica para interconexão com um elemento externo.
Abstract:
A method of fabricating a semiconductor assembly 10 can include providing a semiconductor element 20 having a front surface 21, a rear surface 22, and a plurality of conductive pads 50, forming at least one hole 40 extending at least through a respective one of the conductive pads 50 by processing applied to the respective conductive pad 50 from above the front surface 21, forming an opening 30 extending from the rear surface 22 at least partially through a thickness of the semiconductor element 20, such that the at least one hole 30 and the opening 40 meet at a location between the front and rear surfaces, and forming at least one conductive element 60, 80 exposed at the rear surface 22 for electrical connection to an external device, the at least one conductive element extending within the at least one hole 30 and at least into the opening 40, the conductive element being electrically connected with the respective conductive pad 50.
Abstract:
A microelectronic unit can include a carrier structure having a front surface, a rear surface remote from the front surface, and a recess having an opening at the front surface and an inner surface located below the front surface of the carrier structure. The microelectronic unit can also include a microelectronic element having a top surface adjacent the inner surface, a bottom surface remote from the top surface, and a plurality of contacts at the top surface. The microelectronic unit can also include terminals electrically connected with the contacts of the microelectronic element. The terminals can be electrically insulated from the carrier structure. The microelectronic unit can also include a dielectric region contacting at least the bottom surface of the microelectronic element. The dielectric region can define a planar surface located coplanar with or above the front surface of the carrier structure.
Abstract:
A microelectronic assembly including a first and second microelectronic elements. (12, 14) Each of the microelectronic elements (12, 14) have oppositely-facing first (14, 22) and second surfaces (18, 24) and edges bounding the surfaces. The first microelectronic element (12) is disposed on the second microelectronic element (14) with the second surface (18) of the first microelectronic element (14) facing toward the first surface (22) of the second microelectronic element (14). The first microelectronic element (12) preferably extends beyond at least one edge of the second microelectronic element (14) and the second microelectronic element (14) preferably extends beyond at least one edge of the first microelectronic element (12).
Abstract:
A component 10 can include a substrate 20 having a front surface 22 and a rear surface 21 remote therefrom, an opening 30 extending from the rear surface towards the front surface, and a conductive via 40 extending within the opening. The substrate 20 can have a CTE less than 10 ppm/°C. The opening 30 can define an inner surface 31 between the front and rear surfaces 22, 21. The conductive via 40 can include a first metal layer 41 overlying the inner surface 31 and a second metal region 42 overlying the first metal layer and electrically coupled to the first metal layer. The second metal region 42 can have a CTE greater than a CTE of the first metal layer 41. The conductive via 40 can have an effective CTE across a diameter D of the conductive via that is less than 80% of the CTE of the second metal region 42.
Abstract:
A component 10 can include a substrate 20 having a front surface 22 and a rear surface 21 remote therefrom, an opening 30 extending from the rear surface towards the front surface, and a conductive via 40 extending within the opening. The substrate 20 can have a CTE less than 10 ppm/°C. The opening 30 can define an inner surface 31 between the front and rear surfaces 22, 21. The conductive via 40 can include a first metal layer 41 overlying the inner surface 31 and a second metal region 42 overlying the first metal layer and electrically coupled to the first metal layer. The second metal region 42 can have a CTE greater than a CTE of the first metal layer 41. The conductive via 40 can have an effective CTE across a diameter D of the conductive via that is less than 80% of the CTE of the second metal region 42.
Abstract:
A method for making a microelectronic assembly includes providing a microelectronic element 30 with first conductive elements and a dielectric element 50 with second conductive elements. At least some of either the first conductive elements or the second conductive elements may be conductive posts 40 and other of the first or second conductive elements may include a bond metal 10 disposed between some of the conductive posts 40. An underfill layer 60 may overly some of the first or second conductive elements. At least one of the first conductive elements may be moved towards the other of the second conductive elements so that the posts pierce the underfill layer 60 and at least deform the bond metal 10. The microelectronic element 30 and the dielectric element 50 can be heated to join them together. The height of the posts 40 above the surface may be at least forty percent of a distance between surfaces of the microelectronic element 30 and dielectric element 50.
Abstract:
A microelectronic package includes a lower unit 11 OA having a lower unit substrate with conductive features and a top and bottom surface 64, 66. The lower unit IIOA includes., one or more lower unit chips 112A, 132A overlying the top surface 64 of the' lower unit substrate 62 that are electrically connected to the conductive features 68, 70 of the lower unit substrate 62. The microelectronic package also includes an upper unit 110 including an upper unit substrate having conductive features, top and bottom surfaces and a hole extending between such top and bottom surfaces. The upper unit further includes one or more upper unit chips 112, 132 overlying the top surface of the upper unit substrate and electrically connected to the conductive features of the upper unit substrate by connections extending within the hole 76.
Abstract:
A microelectronic assembly 100 is provided which includes a first element 110 consisting essentially of at least one of semiconductor or inorganic dielectric material having a surface 103 facing and attached to a major surface 104 of a microelectronic element 102 at which a plurality of conductive pads 106 are exposed, the microelectronic element 102 having active semiconductor devices therein. A first opening 111 extends from an exposed surface 118 of the first element 110 towards the surface 103 attached to the microelectronic element 102, and a second opening 113 extends from the first opening 111 to a first one of the conductive pads 106, wherein where the first and second openings meet, interior surfaces 121, 123 of the first and second openings extend at different angles relative to the major surface 104 of the microelectronic element 102. A conductive element 114 extends within the first and second openings 111, 113 and contacts the at least one conductive pad 106.