公开(公告)号：US11885834B2

公开(公告)日：2024-01-30

申请号：US17463112

申请日：2021-08-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lei Ding ,  Srinath Mathur Ramaswamy ,  Dok Won Lee ,  Baher Haroun ,  Wai Lee ,  Steven John Loveless

IPC: G01R15/20 ,  G01R19/10

CPC classification number: G01R15/202 ,  G01R19/10

Abstract: In a described example, a circuit includes a sensor circuit including multiple magnetic field sensors having respective sensor outputs. The magnetic field sensors are configured to provide magnetic field sensor signals at the respective sensor outputs representative of a measure of current flow through a conductive structure. A combiner interface has combiner inputs and a combiner output. The combiner inputs are coupled to the respective sensor outputs. The combiner interface is configured to provide an aggregate sensor measurement at the combiner output responsive to the magnetic field sensor signals, in which the aggregate sensor measurement is decoupled from magnetic fields generated responsive to the current flow through the conductive structure.

公开(公告)号：US10236900B1

公开(公告)日：2019-03-19

申请号：US15836976

申请日：2017-12-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Steven John Loveless ,  Yuguo Wang ,  Tathagata Chatterjee ,  Robert Stanley Grondalski

IPC: H03K5/24 ,  H03M1/10 ,  G01R27/26 ,  H03K21/08

Abstract: An analog-to-digital converter (ADC) comprising successive approximation circuitry, a capacitive analog-to-digital converter (CDAC), and capacitor mismatch measurement circuitry. The successive approximation circuitry is configured to control conversion of an analog signal to a digital value. The CDAC is coupled to the successive approximation circuitry. The CDAC includes a plurality of capacitors. The capacitor mismatch measurement circuitry is coupled to the CDAC. The capacitor mismatch measurement circuitry includes a first oscillator circuit, a second oscillator circuit, and counter circuitry. The first oscillator circuit is configured to oscillate at a frequency determined by a capacitance of one of the capacitors. The second oscillator circuit is configured to generate a predetermined time interval. The counter circuitry is configured to count a number of cycles of oscillation of the first oscillator in the predetermined time interval.