公开(公告)号：WO1997024764A1

公开(公告)日：1997-07-10

申请号：PCT/GB1997000008

申请日：1997-01-02

Applicant: TEXAS INSTRUMENTS INCORPORATED ,  TEXAS INSTRUMENTS LIMITED

Inventor： TEXAS INSTRUMENTS INCORPORATED ,  TEXAS INSTRUMENTS LIMITED ,  ORTHMANN, Kurt ,  MITTERTRAINER, Peter ,  HOFFMANN, Johann

IPC: H01L25/16

CPC classification number: H01L25/16 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2924/01322 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A standard package is provided in which circuit components (10) and non-integrated circuit components (20, 30, 40) are electrically connected together and then overmoulded (70). The components may be coupled together on a lead frame (60). The standard package may provide a desired electrical function by itself or it may be coupled together with other overmoulded packages or additional non-overmoulded electronic components.

Abstract translation: 提供了一种标准封装，其中电路部件（10）和非集成电路部件（20,30,40）电连接在一起，然后被包覆成型（70）。 组件可以在引线框架（60）上耦合在一起。 标准包装可以自己提供期望的电功能，或者可以与其它包覆成型的包装或附加的非包覆成型的电子部件耦合在一起。

公开(公告)号：WO1997012397A1

公开(公告)日：1997-04-03

申请号：PCT/US1996016023

申请日：1996-09-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： TEXAS INSTRUMENTS INCORPORATED

IPC: H01L23/34

CPC classification number: H01L25/0657 ,  H01L23/4922 ,  H01L23/49827 ,  H01L23/5385 ,  H01L24/01 ,  H01L2225/06513 ,  H01L2225/0652 ,  H01L2225/06527 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/3011 ,  H05K3/462 ,  H05K3/4623 ,  H05K2201/0116 ,  H05K2201/09536 ,  H05K2201/09609 ,  H05K2201/10378

Abstract: An assembly of two or more microelectronic parts, wherein electrical and/or thermal interconnection between the parts is achieved by means of multiple, discrete, conductive nanoscopic fibrils (15) or tubules (15) fixed within the pores of an insulating film (16). Such a film is said to have anisotropic electrical conductivity, i.e., Z-axis conductivity, with little or no conductivity in the other directions.

Abstract translation: 两个或多个微电子部件的组件，其中部件之间的电和/或热互连通过固定在绝缘膜（16）的孔内的多个离散的，导电的纳米级原纤（15）或小管（15）来实现， 。 据说这样的膜具有各向异性导电性，即Z轴导电性，在其它方向上几乎没有或没有导电性。

公开(公告)号：WO1996003775A1

公开(公告)日：1996-02-08

申请号：PCT/GB1995001710

申请日：1995-07-20

Applicant: TEXAS INSTRUMENTS INCORPORATED ,  TEXAS INSTRUMENTS LIMITED

Inventor： TEXAS INSTRUMENTS INCORPORATED ,  TEXAS INSTRUMENTS LIMITED ,  HOTCHKISS, Gregory ,  LEVINE, Jules, David ,  SHARROCK, Paul, Ray

IPC: H01L31/18

CPC classification number: H01L31/03529 ,  H01L31/042 ,  H01L31/1804 ,  H01L31/1876 ,  H01L2924/0002 ,  Y02E10/547 ,  Y02P70/521 ,  H01L2924/00

Abstract: An improved method of affixing spheres (4) to a foil matrix (2) is described herein. First, a cell sandwich (32) is prepared. This cell sandwich (32) includes spheres (4) mounted on a foil matrix (2) which are disposed between upper and lower pressure pads (34 and 36). The cell sandwich (32) is then heated (e.g., to about 530 DEG C). The spheres (4) are then affixed to the foil matrix (2) by directing the cell sandwich (32) through a roll press (48) which compresses the heated cell sandwich (32).

Abstract translation: 本文描述了将球体（4）固定到箔基质（2）的改进方法。 首先，准备细胞夹心（32）。 该电池夹层（32）包括安装在箔基体（2）上的球体（4），它们设置在上压力垫和下压力垫（34和36）之间。 然后将电池夹层（32）加热（例如至约530℃）。 然后通过将细胞夹层（32）引导通过压制加热的细胞夹心（32）的辊压机（48）将球体（4）固定到箔基质（2）上。

公开(公告)号：WO1995030227A1

公开(公告)日：1995-11-09

申请号：PCT/GB1995000978

申请日：1995-04-28

Applicant: TEXAS INSTRUMENTS INCORPORATED ,  TEXAS INSTRUMENTS LIMITED

Inventor： TEXAS INSTRUMENTS INCORPORATED ,  TEXAS INSTRUMENTS LIMITED ,  DORNEY, Timothy, Dominic ,  BALISTRERI, Anthony, Michael

IPC: G11C29/00

CPC classification number: G11C29/28

Abstract: An integrated circuit memory device (21) includes plural input/output pins (30, 127 and others) and plural arrays of addressable storage cells (31-46). A set of circuits (51, 68, 70, 71-86, 90) provides access to a unique storage location in each array (31-46) through a given row and column address. A writing circuit (47, 68, 70, 71-86, 91-106, 131-146), designed for test, provides in parallel plural copies of a test data bit. The test data bit is applied through a single pin (30) and a common data-in lead (68), for storage in an addressed storage cell in each of the arrays. A readout circuit (110, 111, 112, 171, 127, 201-216, 131-146) is arranged for reading out the stored test data bit from the addressed storage cell in each of the arrays (31-46). The writing circuit, while in a block write test mode, stores the test data bit on the common data-in lead (68) in a block of address locations in each array (31-46).

Abstract translation: 集成电路存储器件（21）包括多个输入/输出引脚（30,127等）和多个可寻址存储单元阵列（31-46）。 一组电路（51,68,70,71-86,90）通过给定的行和列地址提供对每个阵列（31-46）中唯一存储位置的访问。 设计用于测试的写入电路（47,68,70,71-86,91-106,131-146）并行提供测试数据位的多个副本。 测试数据位通过单个引脚（30）和公共数据输入引线（68）施加，用于存储在每个阵列中的寻址存储单元中。 读出电路（110,111,112,171,127,201-216,131-146）用于从每个阵列（31-46）中的所寻址的存储单元读出存储的测试数据位。 写入电路在块写入测试模式下，将测试数据位存储在每个阵列（31-46）中的地址位置块中的公共数据引入线（68）中。

公开(公告)号：WO1994001816A1

公开(公告)日：1994-01-20

申请号：PCT/GB1993001469

申请日：1993-07-13

Applicant: TEXAS INSTRUMENTS FRANCE ,  TEXAS INSTRUMENTS INCORPORATED ,  CHAUVEL, Gérard ,  LAURENTI, Gilbert ,  CIROUX, Jean ,  WENZINGER, Yves ,  DENT, Peter

Inventor： TEXAS INSTRUMENTS FRANCE ,  TEXAS INSTRUMENTS INCORPORATED

IPC: G06F09/38

CPC classification number: G06F15/7842

Abstract: Processor architecture comprising a central processing unit CPU (2, 4), a program memory (1) and a data memory (3), the central processing unit being functionally composed of a program execution portion (1, 2) and a data processing portion (4), characterised in that, in order to reduce the number of components participating in the constitution of the processor, at least one element (6, 11, 12) of the program execution portion (1, 2) is disposed in the data processing portion (4).

Abstract translation: 处理器架构包括中央处理单元CPU（2,4），程序存储器（1）和数据存储器（3），所述中央处理单元在功能上由程序执行部分（1,2）和数据处理部分 （4），其特征在于，为了减少参与处理器结构的部件的数量，程序执行部分（1,2）的至少一个元件（6,11,12）被布置在数据中 处理部（4）。

公开(公告)号：WO1996004685A1

公开(公告)日：1996-02-15

申请号：PCT/GB1995001857

申请日：1995-08-04

Applicant: TEXAS INSTRUMENTS LIMITED ,  TEXAS INSTRUMENTS INCORPORATED ,  GARNHAM, David, Arthur ,  RUTGERS, Koenraad, Teunis, Francis

Inventor： TEXAS INSTRUMENTS LIMITED ,  TEXAS INSTRUMENTS INCORPORATED

IPC: H01L29/32

CPC classification number: H01L29/66295 ,  H01L21/221 ,  H01L29/1004 ,  H01L29/102 ,  H01L29/32

Abstract: A semiconductor device having two or more p-n junctions, being in particular a bipolar transistor or a thyristor. The device has a gold ion implant (14) in a region of the device between two of or the two p-n junctions, which region is the base (2) in the case of a bipolar transistor, located away from the current carrying active region of the device. The device has a low resistance and may be turned off rapidly because the implanted gold provides recombination centres which act as a sink for carriers drawing them from the active region.

Abstract translation: 具有两个或更多个p-n结的半导体器件，特别是双极晶体管或晶闸管。 器件在两个或两个pn结之间的器件的区域中具有金离子注入（14），在双极晶体管的情况下，该区域是基极（2），位于远离载流有源区 装置。 该器件具有低电阻并且可能被快速关闭，因为注入的金提供复合中心，其用作用于从活性区域吸取它们的载体的汇点。

公开(公告)号：WO1995016266A1

公开(公告)日：1995-06-15

申请号：PCT/EP1994004071

申请日：1994-12-07

Applicant: TEXAS INSTRUMENTS ITALIA SPA ,  TEXAS INSTRUMENTS INCORPORATED ,  IMONDI, Giuliano ,  MENICHELLI, Stefano ,  SANSONE, Carlo

Inventor： TEXAS INSTRUMENTS ITALIA SPA ,  TEXAS INSTRUMENTS INCORPORATED

IPC: G11C07/00

CPC classification number: G11C7/1039

Abstract: A field memory having a distributed architecture is disclosed and in particular a memory arranged in block, wherein each block stores a bit or bits of said word, said bits having a predetermined position within said word. The distributed architecture improves the transfer of data between the input/output buffers and the internal registers of the memory. A data cache and an improved input erasable realisation are also disclosed.

Abstract translation: 公开了具有分布式架构的场存储器，特别是以块为单位布置的存储器，其中每个块存储所述字的位或位，所述位在所述字内具有预定位置。 分布式架构改善了输入/输出缓冲器和存储器的内部寄存器之间的数据传输。 还公开了数据高速缓存和改进的输入可擦除实现。

公开(公告)号：WO1994002894A2

公开(公告)日：1994-02-03

申请号：PCT/GB1993001470

申请日：1993-07-13

Applicant: TEXAS INSTRUMENTS FRANCE ,  TEXAS INSTRUMENTS INCORPORATED ,  CHAUVEL, Gérard ,  WENZINGER, Yves ,  DENT, Peter

Inventor： TEXAS INSTRUMENTS FRANCE ,  TEXAS INSTRUMENTS INCORPORATED

IPC: G06F09/32

CPC classification number: G06F9/3001 ,  G06F9/30094 ,  G06F9/30181 ,  G06F9/325 ,  G06F9/34 ,  G06F9/3804 ,  G06F9/3842 ,  G06F12/04 ,  G06F15/8015 ,  G11C7/00 ,  G11C8/00

Abstract: The invention concerns a data-processing system of the microprocessor type, with two pipeline levels comprising a device of executing an instruction sequence in a repetitive manner, comprising a program counter (74), and a program-address-start register (76) to record the number of the first instruction of the instruction sequence and a repeat counter (70) initialized at the time the first instruction of the instruction sequence is executed. The next-to-last instruction of the instruction sequence to be repeated contains an end-of-loop (EOL) code, which, when the last instruction of the loop is executed, directs that the contents of the program-address-start register (76) be loaded into the program counter (74) as long as the repeat counter is not at zero. The end-of-loop (EOL) code permits an important reduction in the circuits used and an increase in the speed of handling loops.

Abstract translation: 本发明涉及一种微处理器类型的数据处理系统，其中两个流水线级包括以重复方式执行指令序列的装置，包括程序计数器（74）和程序地址开始寄存器（76）， 记录指令序列的第一指令的编号，以及执行指令序列的第一指令时初始化的重复计数器（70）。 要重复的指令序列的最后一条指令包含循环结束（EOL）代码，当执行循环的最后一条指令时，指示程序地址开始寄存器的内容 （76）只要重复计数器不为零就被加载到程序计数器（74）中。 循环（EOL）代码允许重要的减少所使用的电路和提高处理循环的速度。

公开(公告)号：WO1987001508A1

公开(公告)日：1987-03-12

申请号：PCT/US1986001714

申请日：1986-08-25

Applicant: FSI CORPORATION ,  TEXAS INSTRUMENTS INCORPORATED

Inventor： FSI CORPORATION ,  TEXAS INSTRUMENTS INCORPORATED ,  BLACKWOOD, Robert, Stephan ,  BIGGERSTAFF, Rex, Lee ,  CLEMENTS, Luther, Davis ,  CLEAVELIN, Cloves, Rinn

IPC: H01L21/306

CPC classification number: H01L21/31116

Abstract: A process of removing at least a portion of a film from a substrate, such as a wafer of silicon or other similar materials, the film on the substrate typically being an oxide film, maintaining the atmosphere embracing the substrate at near room temperature and at near normal atmospheric pressure, flowing dry inert diluent gas over the substrate, pretreating the film by flowing vapor over the substrate and film flowing an anhydrous reactive gas from a source separate from the source of vapour, over the substrate and film and particularly flowing anhydrous hydrogen halide gas, namely anhydrous hydrogen fluoride gas over the substrate and film to cause the removal of portions of the film, continuing the flow of the reactive gas over the substrate film for typically 5 to 30 seconds, until a controlled amount of film has been removed, terminating the flow of reactive gas and continuing the flow of dry inert diluent gas to stop the removal of film. In the case of non-hydroscopic film on the substrate, the flow of vapor continues during the flow of the reactive gas and is terminated shortly after the termination of the flow of reactive gas.

Abstract translation: 从硅衬底或其他类似材料的衬底去除至少一部分膜的工艺，衬底上的膜通常是氧化膜，保持包围衬底的气氛在接近室温和接近 正常的大气压力，流过干燥的惰性稀释气体在基板上，通过在基板上流动蒸气来预处理膜，以及将来自与蒸气源分离的源的无水反应气体流过衬底和膜，并且特别是流动的无水卤化氢 气体，即在基材和膜上的无水氟化氢气体，以引起膜的部分去除，将反应性气体在基材膜上继续流动通常为5至30秒，直到已经除去受控量的膜， 终止反应气体的流动并继续干燥惰性稀释气体的流动以停止除去膜。 在衬底上的非吸湿膜的情况下，在反应气体的流动期间蒸汽的流动继续，并且在反应气体流动结束后不久就终止。